Rainbow Electronics DS2172 - Manual (Page 6)

DS2172
031197 6/20
DS2172 REGISTER MAP Table 2
ADDRESS R/W REGISTER NAME
00 R/W Pattern Set Register 3.
01 R/W Pattern Set Register 2.
02 R/W Pattern Set Register 1.
03 R/W Pattern Set Register 0.
04 R/W Pattern Length Register.
05 R/W Polynomial Tap Register.
06 R/W Pattern Control Register.
07 R/W Error Insert Register.
08 R Bit Counter Register 3.
09 R Bit Counter Register 2.
0A R Bit Counter Register 1.
0B R Bit Counter Register 0.
0C R Bit Error Counter Register 3.
0D R Bit Error Counter Register 2.
0E R Bit Error Counter Register 1.
0F R Bit Error Counter Register 0.
10 R Pattern Receive Register 3.
11 R Pattern Receive Register 2.
12 R Pattern Receive Register 1.
13 R Pattern Receive Register 0.
14 R Status Register.
15 R/W Interrupt Mask Register.
1C R/W Test Register (see note 1)
NOTE:
1. The Test Register must be set to 00 hex to insure
proper operation of the DS2172.
2.0 PARALLEL CONTROL INTERFACE
The DS2172 is controlled via a multiplexed bi–direc-
tional address/data bus by an external microcontroller
or microprocessor. The DS2172 can operate with either
Intel or Motorola bus timing configurations. If the BTS
pin is tied low, Intel timing will be selected; if tied high,
Motorola timing will be selected. All Motorola bus sig-
nals are listed in parenthesis (). See the timing dia-
grams in the A.C. Electrical Characteristics for more
details. The multiplexed bus on the DS2172 saves pins
because the address information and data information
share the same signal paths. The addresses are pres-
ented to the pins in the first portion of the bus cycle and
data will be transferred on the pins during second por-
tion of the bus cycle. Addresses must be valid prior to
the falling edge of ALE(AS), at which time the DS2172
latches the address from the AD0 to AD7 pins. Valid
write data must be present and held stable during the
later portion of the DS or WR pulses. In a read cycle, the
DS2172 outputs a byte of data during the latter portion of
the DS or RD pulses. The read cycle is terminated and
the bus returns to a high impedance state as RD transi-
tions high in Intel timing or as DS transitions low in Moto-
rola timing. The DS2172 can also be easily connected
to non–multiplexed buses. RCLK and TCLK are used to
update counters and load transmit and receive pattern
registers. At slow clock rates, sufficient time must be
allowed for these port operations.
3.0 PATTERN SET REGISTERS
The Pattern Set Registers (PSR) are loaded each time a
new pattern (whether it be pseudorandom or repetitive)
is to be generated. When a pseudorandom pattern is
generated, all four PSRs must be loaded with FF Hex.
When a repetitive pattern is to be created, the four PSRs
are loaded with the pattern that is to be repeated.
Please see Tables 4 and 5 for some programming
examples.