Rainbow Electronics DS2182A - Manual (Page 8)

DS2182A
041995 8/22
RSR1: RECEIVE STATUS REGISTER 1 Figure 8
(MSB) (LSB)
8ZD 16ZD RCL RYEL RLOS B8ZSD RBL COFA
SYMBOL POSITION NAME AND DESCRIPTION
8ZD RSR1.7 8 Zero Detect. Set when a string of eight consecutive 0s has been re-
ceived at RPOS and RNEG.
16ZD RSR1.6 16 Zero Detect. Set when a string of 16 consecutive 0s has been received
at RPOS and RNEG.
RCL RSR1.5 Receive Carrier Loss. Set when a string of 192 consecutive 0s has been
received at RPOS and RNEG. Cleared when 14 or more ones out of 112
possible bit positions are received.
RYEL RSR1.4 Receive Yellow Alarm. Set when yellow alarm is detected. The format of
yellow alarm is determined by RCR2.3 and RCR2.4.
RLOS RSR1.3 Receive Loss of Sync. Set when resync is in progress.
B8ZSD RSR1.2 B8ZS Code Word Detect. Set when a B8ZS code word is received at
RPOS and RNEG independent of whether the B8ZS mode is enabled or
not (RCR2.2).
RBL RSR1.1 Receive Blue Alarm. Set when over a 3 ms window, 5 or less zeros are
received. Cleared when over a 3 ms window, 6 or more zeros are received.
COFA RSR1.0 Change of Frame Alignment. Set when the last resync resulted in a
change of frame or multiframe alignment.
NOTE:
1. Alarms 8ZD and 16ZD are cleared on the next occurrence of a 1 at RPOS and RNEG.
RECEIVE STATUS REGISTERS
The receive status registers (RSR1 and RSR2) can be
used in either a polled or an interrupt configuration. In a
polled configuration, the user reads the RSR at regular
intervals to check for alarms. In an interrupt configura-
tion, the user monitors the INT pin. When the INT pin
goes low, an alarm condition has occurred and has been
reported in one of the RSRs. The processor can then
read the RSRs to find which bits have been set. All of the
bits in the RSRs operate in a latched fashion. That is,
once set, they remain set until read. The bits in the RSR
are cleared when read unless the read was performed in
the burst mode or the alarm condition still exists.
YELLOW ALARM
193S BIT 2. If RCR2.4 = 0 and RCR2.3 = 0, then the
DS2182A examines bit 2 of all incoming channels for
the presence of a yellow alarm. If bit 2 is set to 0 in 256
consecutive channels, then the reception of a yellow
alarm is declared. The alarm is considered cleared
when the first channel with bit 2 set to a 1 is received.
193S S-BIT. If RCR2.4 = 0 and RCR2.3 = 1, then the
DS2182A examines the S-bit position of frame 12 for the
presence of a yellow alarm. The DS2182A declares the
presence of a yellow alarm on the first occurrence of the
S-bit in frame 12 being set to 1. The alarm is considered
cleared when this S-bit returns to 0.
193E FDL. If RCR2.4 = 1, then the DS2182A examines
the FDL for a repeating 00FF pattern. If this pattern is
received in the FDL 16 consecutive times without error,
then a yellow alarm is declared. The alarm is consid-
ered cleared as soon as any pattern other than 00FF is
received.