Rainbow Electronics DS2143Q - Manual (Page 11)

DS2143/DS2143Q
031397 11/40
TG802 CCR.5 Transmit G.802 Enable. See Section 13 for details.
0 = do not force TCHBLK high during bit 1 of timeslot 26
1 = force TCHBLK high during bit 1 of timeslot 26
TCRC4 CCR.4 Transmit CRC4 Enable.
0 = CRC4 disabled
1 = CRC4 enabled
RSM CCR.3 Receive Signaling Mode Select.
0 = CAS signaling mode
1 = CCS signaling mode
RHDB3 CCR.2 Receive HDB3 Enable.
0 = HDB3 disabled
1 = HDB3 enabled
RG802 CCR.1 Receive G.802 Enable. See Section 13 for details.
0 = do not force RCHBLK high during bit 1 of timeslot 26
1 = force RCHBLK high during bit 1 of timeslot 26
RCRC4 CCR.0 Receive CRC4 Enable.
0 = CRC4 disabled
1 = CRC4 enabled
LOCAL LOOPBACK
When CCR.7 is set to a one, the DS2143 will enter a
Local LoopBack (LLB) mode. This loopback is useful in
testing and debugging applications. In LLB, the
DS2143 will loop data from the transmit side back to the
receive side. This loopback is synonymous with replac-
ing the RCLK input with the TCLK signal, and the RPOS/
RNEG inputs with the TPOS/TNEG outputs. When LLB
is enabled, the following will occur;
1. data at RPOS and RNEG will be ignored
2. all receive side signals will take on timing synchro-
nous with TCLK instead of RCLK
3. all functions are available.
4.0 STATUS AND INFORMATION REGISTERS
There is a set of four registers that contain information
on the current real time status of the DS2143, Status
Register 1 (SR1), Status Register 2 (SR2), Receive
Information Register (RIR), and Synchronizer Status
Register (SSR). When a particular event has occurred
(or is occurring), the appropriate bit in one of these three
registers will be set to a one. All of the bits in these regis-
ters operate in a latched fashion (except for the SSR).
This means that if an event occurs and a bit is set to a
one in any of the registers, it will remain set until the user
reads that bit. The bit will be cleared when it is read and
it will not be set again until the event has occurred again
or if the alarm(s) is still present.
The user will always precede a read of the SR1, SR2,
and RIR registers with a write. The byte written to the
register will inform the DS2143 which bits the user
wishes to read and have cleared. The user will write a
byte to one of these three registers, with a one in the bit
positions he or she wishes to read and a zero in the bit
positions he or she does not wish to obtain the latest
information on. When a one is written to a bit location,
the read register will be updated with current value and it
will be cleared. When a zero is written to a bit position,
the read register will not be updated and the previous
value will be held. A write to the status and information
registers will be immediately followed by a read of the
same register. The read result should be logically
AND’ed with the mask byte that was just written and this
value should be written back into the same register to
insure that the bit does indeed clear. This second write
is necessary because the alarms and events in the sta-
tus registers occur asynchronously in respect to their
access via the parallel port. This scheme allows an
external microcontroller or microprocessor to individu-
ally poll certain bits without disturbing the other bits in
the register. This operation is key in controlling the
DS2143 with higher order software languages.
The SSR register operates differently than the other
three. It is a read only register and it reports the status of
the synchronizer in real time. This register is not latched
and it is not necessary to precede a read of this registers
with a write.