Rainbow Electronics BD5323G_FVE - Manual (Page 5)

Operating explanation
•When V DD is equal to or more than the release voltage (V DET + V DET ), CT pin voltage becomes V DD
(External capacitor is in charging mode.) and output V OUT is in "H" mode. (Nch output transistor Q1 is OFF,
Pch output transistor Q2 is ON.) When V DD is gradually decreased, Q3 connected to CT pin in the detection
voltage (V DET ) switches OFF to ON, external capacitor is discharged, and CT pin voltage becomes
decreased. When the CT pin voltage is lower than the threshold voltage of next inverter, output (V OUT ) turns
"L". (Nch output transistor Q1 is ON, Pch output transistor Q2 is OFF.)
• When V DD is equal to or lower than the detection voltage (V DET ), CT pin voltage is L voltage (External
capacitor is in discharging mode and Q3 is ON), output V OUT is in "L" mode. When V DD is gradually
increased, Q3 is OFF in the release voltage (V DET + V DET ) and CT pin external capacitor becomes to be
charged through resistor R1 in the IC. When the CT pin voltage is more than the threshold voltage of next
inverter, output (V
OUT ) goes from "L" to "H". (Nch output transistor Q1 is OFF, Pch output transistor Q2 is
ON.) Delay time is the time when output V OUT goes from "L" to "H" after the V DD is more than the release
voltage. (V DET + V DET ) Delay time can be set freely by the CT pin external capacitor. (Usage is shown at P10)
Ex.) For both open drain type (Fig.7) and CMOS output type (Fig.8), detection voltage and release voltage are
threshold voltage. When voltage applied to V
DD pin reaches each threshold voltage, V OUT pin voltage goes
“H” “L” or “L” “H’. BD52XXG/FVE and BD53XXG/FVE incorporate delay time circuit that can set delay time
by the external capacitor when output goes“L” “H”. BD52XXG/FVE series are open drain types and pull-up
resistor must be connected to V
DD , or other power supply. (In this case, output (V OUT ) H voltage is V DD , or
other power supply voltage.)
Ex.) The relation between input voltage V DD and output voltage V OUT when V DD is increased and decreased
is shown below. (Circuit is shown in Fig7, Fig.8)
• SWEEP DOWN for V DD
• SWEEP UP for V DD
•Some hysteresis is given such a way that the release voltage is the detection voltageX(1.05 Typ.).
• The output becomes inconsistent if the V DD is equal to or lower than the operating limit voltage.
R1
R2
R3
Q3
Q1
V ref
Vout
V DD
V DD
Reset
CT
GND
GND
Fig.7 (BD52XX type Internal block diagram) Fig.8 (BD53XX Internal block diagram)
Timing waveform
If the V DD is equal to or lower than the operating limit
voltage (V OPL ) at power-up, the output is inconsistent.
If the V DD goes below the detection voltage (V DET ) at
power-down or instantaneous power failure, V OUT turns L
with a delay of T PHL . See Fig.16 for the reference waveform.
The potential difference between the detection voltage and
the release voltage is called hysteresis ( V
DET ).
The products are designed so as to prevent power supply
fluctuation within this hysteresis from causing fluctuation in
output in order to avoid malfunction due to noise.
When the V DD is equal to or more than reset release voltage
(V DET + V DET ), V OUT goes from "L" to "H" with a delay
of T PLH set by the capacitor that is connected to CT pin.
When the V DD is equal to or more than the V OPL and the
V DD is equal to or more than the reset release voltage
(V DET + V DET ), CT pin voltage (V CT ) is "L" and output
(V OUT ) is also "L".
Fig.9
R1
R2
R3
Q1 Q3
Q2 V DD
Vref
Reset
Vout
CT
V DD
GND
2
1
3
4
5/15
Voltage detectors
BD52XXG/FVE
BD53XXG/FVE
2 1 3 4
V DD
V DD
1/2 V DD
V DD
V OUT
V CT
V IN
V DET
0V
V OPL
V DET + V DET
T PHL
T PLH T PLH
Rev.A