Rainbow Electronics DS2132A_Q User Manual
Page 2
DS2132A/Q
041295 2/17
PIN DESCRIPTION Table 1
PIN
SYMBOL
TYPE
DESCRIPTION
3,4,12,14,21,22
GND
-
Ground. Tie to system ground.
6,7,8,9,10,11,28
VCC
-
Positive Supply. Tie to system +5 volt supply.
1
PD
O
Power-Down Active Low. Will toggle low during Power-
Down mode.
5
PD
O
Power-Down Active High. Will toggle high during Power-
Down mode.
15
NC
-
No Connect. Do not connect any signal to this pin.
2
RST
I
Reset. When this pin is low, the internal DSP algorithm is
in a reset state. On power-up, this pin should be held low
for at least 100 ms after MCLK is stable.
13
MCLK
I
Master Processing Clock. The clock used for the internal
DSP engine. Should be in the range of 12 to 16 MHz.
MCLK can be asynchronous to any other clock signal on
the DS2132A. The duty cycle should be 50% (
±
5%).
16
CDIN
I
Compressed Data Port Input. Serial input for com-
pressed audio data or DS2132A commands. Samples on
the falling edges of CLK. The compressed data is expand-
ed to 8-bit PCM which is output on PCMOUT.
17,26
CLK
I
Clock. This clock is used to sample data at CDIN and
PCMIN and output data at CDOUT and PCMOUT. CLK
must be synchronous with FS. See Figure 3.
18,25
FS
I
Frame Sync. This input must be an 8 KHz clock with a
pulse width high time of one to nine CLK cycles for proper
operation. See Figure 3.
19
TRI_OUT
O
CDOUT Tri-state Control Out. This output should be tied
to the TRI_IN pin (pin 23) for proper operation; will be low
when CDOUT is active.
20
CDOUT
O
Compressed Data Port Output. Serial output for com-
pressed audio data or status information, updated on the
rising edge of CLK.
23
TRI_IN
I
CDOUT Tri-state Control In. This input should be tied to
the TRI_OUT pin (pin 19) for proper operation. If this pin is
forced high, CDOUT will not go active.
24
PCMOUT
O
PCM Port Output. Output for expanded data which is in
the standard 8-bit
µ
-law format. Data is updated on the
rising edges of CLK.
27
PCMIN
I
PCM Port Input. Input for the 8-bit serial
µ
-law PCM data
which would normally be supplied by a codec/filter device.
Data is sampled on the falling edges of CLK.
FUNCTIONAL DESCRIPTION
A typical digital answering machine using the DS2132A
is shown in Figure 1. The system consists of a standard
telephone CODEC (COder-DECoder) device, the
DS2132A, a microcontroller, and a bank of DRAM. The
implementation shown is with a Hitachi CODEC and a
8051-type microcontroller but a wide variety of
CODECs and microcontrollers can be used with the
DS2132A. It is only important that the CODEC have se-
rial digital I/O and have
µ
-law (“Mu” law) companding.
Table 2 lists some CODECs that will work with the
DS2132A. There is a separate Application Note that ex-
plains how to connect these CODECs to the DS2132A.