Rainbow Electronics AT90LS8535 - Manual (Page 45)

45
AT90S/LS8535
1041H–11/01
Timer/Counter2 in PWM Mode When the PWM mode is selected, Timer/Counter2 and the Output Compare Register
(OCR2) form an 8-bit, free-running, glitch-free and phase correct PWM with outputs on
the PD7(OC2) pin. Timer/Counter2 acts as an up/down counter, counting up from $00 to
$FF, where it turns and counts down again to zero before the cycle is repeated. When
the counter value matches the contents of the Output Compare Register, the PD7(OC2)
pin is set or cleared according to the settings of the COM21/COM20 bits in the
Timer/Counter2 Control Register (TCCR2). Refer to Table 19 for details.
Note that in PWM mode, the Output Compare Register is transferred to a temporary
location when written. The value is latched when the Timer/Counter reaches $FF. This
prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsyn-
chronized OCR2 write. See Figure 35 for an example.
Figure 35. Effects of Unsynchronized OCR Latching
During the time between the write and the latch operation, a read from OCR2 will read
the contents of the temporary location. This means that the most recently written value
always will read out of OCR2.
When the OCR register (not the temporary register) is updated to $00 or $FF, the PWM
output changes to low or high immediately according to the settings of COM21/COM20.
This is shown in Table 20.
Table 19. Compare Mode Select in PWM Mode
COM21 COM20 Effect on Compare Pin
0 0 Not connected
0 1 Not connected
1 0 Cleared on compare match, up-counting. Set on compare match, down-
counting (non-inverted PWM).
1 1 Cleared on compare match, down-counting time-out. Set on compare
match, up-counting (inverted PWM).
Table 20. PWM Outputs OCR2 = $00 or $FF
COM21 COM20 OCR2 Output PWM2
1 0 $00 L
Counter Value
Compare Value
PWM Output
Synchronized OCR Latch
Counter Value
Compare Value
PWM Output
Unsynchronized OCR Latch Glitch
Compare Value changes
Compare Value changes