Rainbow Electronics ADC11DL066 - Manual (Page 16)

Functional Description
Operating on a single +3.3V supply, the ADC11DL066 uses
a pipeline architecture and has error correction circuitry to
help ensure maximum performance. The differential analog
input signal is digitized to 11 bits. The user has the choice of
using an internal 1.0 Volt stable reference or using an exter-
nal reference. Any external reference is buffered on-chip to
ease the task of driving that pin.
The output word rate is the same as the clock frequency,
which can be between 15 MSPS and 75 MSPS (typical) with
fully specified performance at 66 Msps. The analog input for
both channels is acquired at the rising edge of the clock and
the digital data for a given sample is delayed by the pipeline
for 6 clock cycles. A choice of Offset Binary or Two’s Comple-
ment output format is selected with the OF pin.
A logic high on the power down (PD) pin reduces the con-
verter power consumption to 75 mW.
Applications Information
1.0 OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC11DL066:
3.0V ≤ V
A
≤ 3.6V
V
D
= V
A
2.4V ≤ V
DR
≤ V
D
15 MHz ≤ f
CLK
≤ 75 MHz
0.8V ≤ V
REF
≤ 1.5V
0.5V ≤ V
CM
≤ 1.8V
1.1 Analog Inputs
There is one reference input pin, V
REF
, for use of an optional
external reference. The ADC11DL066 has two analog signal
input pairs, V
IN
A+ and V
IN
A- for one converter and V
IN
B+
and V
IN
B- for the other converter. Each pair of pins forms a
differential input pair.
1.2 Reference Pins
The ADC11DL066 is designed to operate with a 1.0V refer-
ence, but performs well with reference voltages in the range
of 0.8V to 1.5V. Lower reference voltages will decrease the
signal-to-noise ratio (SNR) of the ADC11DL066. Increasing
the reference voltage (and the input signal swing) beyond
1.5V may degrade THD for a full-scale input, especially at
higher input frequencies.
It is important that all grounds associated with the reference
voltage and the analog input signal make connection to the
ground plane at a single, quiet point to minimize the effects
of noise currents in the ground path.
The ADC11DL066 will perform well with reference voltages
up to 1.5V for full-scale input frequencies up to 10 MHz.
However, more headroom is needed as the input frequency
increases, so the maximum reference voltage (and input
swing) will decrease for higher full-scale input frequencies.
The six Reference Bypass Pins (V
RP
A, V
RM
A, V
RN
A, V
RP
B,
V
RM
B and V
RN
B) are made available for bypass purposes.
The V
RM
A and V
RM
B pins should each be bypassed to
ground with a 0.1 µF capacitor. A series 1.5 Ω resistor (5%)
and 1.0 µF capacitor ( ± 20%) should be placed between the
V
RP
A and V
RN
A pins and between the V
RP
B and V
RN
B pins,
as shown in Figure 4. This configuration is necessary to
avoid reference oscillation, which could result in reduced
SFDR and/or SNR.
Smaller capacitor values than those specified will allow
faster recovery from the power down mode, but may result in
degraded noise performance. DO NOT LOAD these pins.
Loading any of these pins may result in performance degra-
dation.
The nominal voltages for the reference bypass pins are as
follows:
V
RM
= V
A
/ 2
V
RP
= V
RM
+ V
REF
/ 2
V
RN
= V
RM
− V
REF
/ 2
The V
RM
pins may be used as common mode voltage (V
CM
)
sources for the analog input pins as long as no d.c. current is
drawn from them. However, because the voltages at the V
RM
pins are half that of the V
A
supply pin, using these pins for
common mode voltage sources will result in reduced input
headroom (the difference between the V
A
supply voltage
and the peak signal voltage at either analog input) and the
possibility of reduced THD and SFDR performance. For this
reason, it is recommended that V
A
always exceed V
REF
by at
least 2 Volts when using the V
RM
pins as V
CM
sources. For
high input frequencies it may be necessary to increase this
headroom to maintain THD and SFDR performance.
User choice of an on-chip or external reference voltage is
provided. The internal 1.0 Volt reference is in use when the
the INT/EXT REF pin is at a logic low, regardless of any
voltage applied to the V
REF
pin. When the INT/EXT REF pin
is at a logic high, the voltage at the V
REF
pin is used for the
voltage reference. Optimum ADC dynamic performance is
obtained when the reference voltage is in the range of 0.8V
to 1.5V. When an external reference is used, the V
REF
pin
should be bypassed to ground with a 0.1 µF capacitor close
to the reference input pin. There is no need to bypass the
V
REF
pin when the internal reference is used.
There is no direct access to the internal reference voltage.
However the nominal value of the reference voltage,
whether the internal or an external reference is used, is
approximately equal to V
RP
− V
RN
.
1.3 Signal Inputs
The signal inputs are V
IN
A+ and V
IN
A− for one ADC and
V
IN
B+ and V
IN
B− for the other ADC . The input signal, V
IN
, is
defined as
V
IN
A = (V
IN
A+) – (V
IN
A−)
for the "A" converter and
V
IN
B = (V
IN
B+) – (V
IN
B−)
for the "B" converter. Figure 2 shows the expected input
signal range. Note that the common mode input voltage,
V
CM
, should be in the range of 0.5V to 1.8V with a nominal
value of 1.6V.
The peaks of the individual input signals should each never
exceed the voltage described as
Peak Input Voltage = V
A
– 1.0V
to maintain THD and SINAD performance.
The ADC11DL066 performs best with a differential input
signal with each input centered around a common mode
voltage, V
CM
. The peak-to-peak voltage swing at each ana-
log input pin should not exceed the value of the reference
voltage or the output data will be clipped.
The two input signals should be exactly 180˚ out of phase
from each other and of the same amplitude. For single
frequency inputs, angular errors result in a reduction of the
effective full scale input. For complex waveforms, however,
angular errors will result in distortion.
ADC1
1DL066
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