Rainbow Electronics DS1372 - Manual (Page 8)

DS1372
Status Register (08h)
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit
indicates that the oscillator either is stopped or was
stopped for some period of time and may be used to
judge the validity of the timekeeping data. This bit is set
to logic 1 anytime the oscillator stops. The following are
examples of conditions that can cause the OSF bit to
be set:
1) The first time power is applied.
2) The voltage present on V CC is insufficient to sup-
port oscillation.
3) The EOSC bit is turned off.
4) External influences on the crystal (i.e., noise, leak-
age, etc.) exist.
This bit remains at logic 1 until written to logic 0.
Bits 6 to 1: These bits always read back as logic 0.
Bit 0: Alarm Flag (AF). A logic 1 in the AF bit indicates
that the alarm counter reached zero. If the AIE and
INTCN bits are both set to logic 1, the SQW/INT pin
goes low and remains low until AF is written to logic 0.
This bit can only be written to logic 0. Attempting to
write logic 1 leaves the value unchanged.
ID Register
A unique 64-bit lasered serial number is located in the
address range 09h–10h. This serial number is divided
into three parts. The first byte in register 09h contains a
model number to identify the DS1372 device type.
Registers 0Ah–0Fh contain a unique binary number.
Register 10h contains a CRC byte used to validate the
data in registers 09h–0Fh. All eight bytes of the serial
number are read-only registers. The CRC byte is gener-
ated with the polynomial equal to x
8 + x 5 + x 4 + 1 (see
Figure 3).
The DS1372 is manufactured such that no two devices
contain an identical number in locations 0Ah–0Fh.
I 2 C Serial Data Bus
The DS1372 supports a bidirectional I 2 C serial bus and
data transmission protocol (Figure 4). A device that
sends data onto the bus is defined as a transmitter,
and a device receiving data is defined as a receiver.
The device that controls the message is called a mas-
ter. The devices that are controlled by the master are
slaves. The bus must be controlled by a master device
that generates the serial clock (SCL), controls the
bus access, and generates the START and STOP
8 _______________________________________________________________________________________
Bit # 7 6 5 4 3 2 1 0
Name OSF 0 0 0 0 0 0 AF
Reset 1 0 0 0 0 0 0 0
Status Register (08h)
1ST
STAGE
2ND
STAGE
3RD
STAGE
4TH
STAGE
7TH
STAGE
8TH
STAGE
6TH
STAGE
5TH
STAGE
X 0 X 1 X 2 X 3 X 4
POLYNOMIAL = X 8 + X 5 + X 4 + 1
INPUT DATA
X 5 X 6 X 7 X 8
Figure 3. CRC Byte Polynomial
I
2
C, 32-Bit, Binary Counter Clock with 64-Bit ID