Rainbow Electronics ADC11L066 - Manual (Page 20)

Functional Description
Operating on a single +3.3V supply, the ADC11L066 uses a
pipeline architecture and has error correction circuitry to help
ensure maximum performance.
Differential analog input signals are digitized to 11 bits. Each
analog input signal should have a peak-to-peak voltage
equal to the input reference voltage, V
REF
, be centered
around a common mode voltage, V
CM
and be 180˚ out of
phase with each other. Table 1. Input to Output Relationship-
–Differential
Input and Table 2. Input to Output
Relationship–Single-Ended Input indicate the input to output
relationship of the ADC11L066. Biasing one input to V
CM
and
driving the other input with its full range signal results in a 6
dB reduction of the output range, limiting it to the range of
1 ⁄
4
to 3 ⁄
4
of the minimum output range obtainable if both inputs
were driven with complimentary signals. Section 1.3 explains
how to avoid this signal reduction.
TABLE 1. Input to Output Relationship–Differential
Input
V
IN+
V
IN−
Output
V
CM
−0.5* V
REF
V
CM
+0.5* V
REF
000 0000 0000
V
CM
−0.25* V
REF
V
CM
+0.25* V
REF
010 0000 0000
V
CM
V
CM
100 0000 0000
V
CM
+0.25* V
REF
V
CM
−0.25* V
REF
110 0000 0000
V
CM
+0.5* V
REF
V
CM
−0.5* V
REF
111 1111 1111
TABLE 2. Input to Output Relationship–Single-Ended
Input
V
IN+
V
IN−
Output
V
CM
−V
REF
V
CM
000 0000 0000
V
CM
−0.5* V
REF
V
CM
010 0000 0000
V
CM
V
CM
100 0000 0000
V
CM
+0.5* V
REF
V
CM
110 0000 0000
V
CM
+V
REF
V
CM
111 1111 1111
The output word rate is the same as the clock frequency,
which can be between 10 MSPS and 80 MSPS (typical). The
analog input voltage is acquired at the rising edge of the
clock and the digital data for that sample is delayed by the
pipeline for 6 clock cycles.
A logic high on the power down (PD) pin reduces the con-
verter power consumption to 50 mW.
Applications Information
1.0 OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC11L066:
3.0 V ≤ V
A
≤ 3.6V
V
D
= V
A
1.8V ≤ V
DR
≤ V
D
10 MHz ≤ f
CLK
≤ 80 MHz
0.8V ≤ V
REF
≤ 1.5V
0.5V ≤ V
CM
≤ 1.5V
1.1 Analog Inputs
The ADC11L066 has two analog signal inputs, V
IN
+ and
V
IN
−. These two pins form a differential input pair. There is
one reference input pin, V
REF
.
1.2 Reference Pins
The ADC11L066 is designed to operate with a 1.0V refer-
ence, but performs well with reference voltages in the range
of 0.8V to 1.5V. Lower reference voltages will decrease the
signal-to-noise ratio (SNR) of the ADC11L066. Increasing
the reference voltage (and the input signal swing) beyond
1.5V will degrade THD for a full-scale input. It is very impor-
tant that all grounds associated with the reference voltage
and the input signal make connection to the analog ground
plane at a single point to minimize the effects of noise
currents in the ground path.
The ADC11L066 will perform well with reference voltages up
to 1.5V for full-scale input frequencies up to 10 MHz. How-
ever, more headroom is needed as the input frequency
increases, so the maximum reference voltage (and input
swing) will decrease for higher full-scale input frequencies.
The three Reference Bypass Pins (V
RP
, V
RM
and V
RN
) are
made available for bypass purposes only. These pins should
each be bypassed to ground with a 0.1 µF capacitor. Smaller
capacitor values will allow faster recovery from the power
down mode, but may result in degraded noise performance.
DO NOT LOAD these pins. Loading any of these pins may
result in performance degradation.
The nominal voltages for the reference bypass pins are as
follows:
V
RM
= V
A
/ 2
V
RP
= V
RM
+ V
REF
/ 2
V
RN
= V
RM
− V
REF
/ 2
The V
RM
pin may be used as a common mode voltage
source (V
CM
) for the analog input pins as long as no d.c.
current is drawn from it. However, because the voltage at
this pin is half that of the V
A
supply pin, using these pins for
a common mode source will result in reduced input head-
room (the difference between the V
A
supply voltage and the
peak signal voltage at either analog input) and the possibility
of reduced THD and SFDR performance. For this reason, it
is recommended that V
A
always exceed V
REF
by at least 2
Volts. For high input frequencies it may be necessary to
increase this headroom to maintain THD and SFDR perfor-
mance. Alternatively, use V
RN
for a V
CM
source.
1.3 Signal Inputs
The signal inputs are V
IN
+ and V
IN
−. The input signal, V
IN
, is
defined as
V
IN
= (V
IN
+) – (V−)
Figure 2 shows the expected input signal range.
Note that the nominal input common mode voltage is V
REF
and the nominal input signals each run between the limits of
V
REF
/2 and 3V
REF
/2. The Peaks of the input signals should
never exceed the voltage described as
Peak Input Voltage = V
A
− 0.8
to maintain dynamic performance.
The ADC11L066 performs best with a differential input with
each input centered around a common mode voltage, V
CM
(minimum of 0.5V). The peak-to-peak voltage swing at both
V
IN
+ and V
IN
− should not exceed the value of the reference
voltage or the output data will be clipped.
ADC1
1L066
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