Rainbow Electronics ADC12081 - Manual (Page 16)

Applications Information
(Continued)
7.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 300mV beyond the supply rails (more than
300mV below the ground pins or 300mV above the supply
pins). Exceeding these limits on even a transient basis may
cause faulty or erratic operation. It is not uncommon for high
speed digital circuits (e.g., 74F and 74AC devices) to exhibit
undershoot that goes more than a volt below ground above
the power supply. A resistor of about 50 to 100
Ω in series
with the offending digital input will eliminate the problem.
Care should be taken not to overdrive the inputs of the
ADC12081 with a device that is powered from supplies
outside the range of the ADC12081 supply. Such practice
may lead to conversion inaccuracies and even to device
damage.
Attempting to drive a high capacitance digital data bus.
Capacitive loading on the digital outputs causes instanta-
neous digital currents to flow from the V
D
I/O supply into the
DGND I/O ground plane. These large charging current
spikes can couple into the analog section, degrading dy-
namic performance. Adequate bypassing and maintaining
separate analog and digital ground planes will reduce this
problem. The digital data outputs should be buffered (with
74ACQ541, for example). Dynamic performance can also be
improved by adding series resistors at each digital output,
close to the ADC12081, reducing the energy coupled back
into the converter output pins by limiting the output slew rate.
A reasonable value for these resistors is 47
Ω.
Using an inadequate amplifier to drive the analog input.
The analog input circuits of the ADC12081 place a switched
capacitor load on the input signal source. Therefore the
amplifier used to drive the ADC12081 must have a low
impedance output and adequate bandwidth to avoid distor-
tion of the input signal.
Operating with the reference pins outside of the speci-
fied range. As mentioned in section 1.1, V
REF
should be in
the range of 1.8V ≤ V
REF
≤ 2.2V. Operating outside of these
limits could lead to signal distortion.
Using a clock source with excessive jitter, using exces-
sively long clock signal trace, or having other signals
coupled to the clock signal trace. This will cause the
sampling interval to vary, causing excessive output noise
and a reduction in SNR performance.
ADC12081
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