Rainbow Electronics BR24C21FV - Manual (Page 10)

BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV
Memory ICs
RANDOM READ
SLAVE
ADDRESS
SDA
LINE
S
T
A
R
T
1 1 0 0 ∗ ∗ ∗
R
/
W
W
R
I
T
E
Fig.18 RANDOM READ CYCLE TIMING
S
T
O
P
A
C
K
R
E
A
D
DATA(n)
SLAVE
ADDRESS
S
T
A
R
T
R
/
W
A
C
K
1 1 0 0
∗ ∗ ∗
D7 D0
WA
0
WORD
ADDRESS(n)
A
C
K
WA
6
∗
A
C
K
•Random read operation allows the master to access any memory location. This operation involves a two-step
process. First, the master issues a write command which includes the start condition and the slave address field (with
R / W set to “0”) followed by the address of the word to be read. This procedure sets the internal address counter of
the BR24C21, BR24C21F, BR24C21FJ and BR24C21FV to the desired address. After the word address
acknowledge is received by the master, the master immediately reissues a start condition followed by the slave
address field with R / W the set to “1”. The device will respond with an acknowledge and then transmit the 8-data bits
stored at the addressed location. If the master does not acknowledge the transmission but does generate the stop
condition, at this point BR24C21, BR24C21F, BR24C21FJ and BR24C21FV discontinue transmission.
SEQUENTIAL READ
S
T
A
R
T
SLAVE
ADDRESS
R
/
W
A
C
K A
C
K A
C
K A
C
K
R
E
A
D
DATA(n) DATA(n + x)
SDA
LINE
1 1 0 0 ∗ ∗ ∗ D7 D7 D0 D0
S
T
O
P
Fig.19 SEQUENTIAL READ CYCLE TIMING
(Current Read)
•During the sequential read operation, the internal address counter of the BR24C21, BR24C21F, BR24C21FJ and
BR24C21FV automatically increments with each acknowledge received ensuring the data from address n will be
followed with the data from n+1. For read operations, all bits of the address counter are incremented allowing the
entire array to be read during a single operation. When the counter reaches the top of the array, it will “roll over” to the
bottom of the array and continue to transmit the data.
•The sequential read operation can be performed with both current read and random read.