Rainbow Electronics DS1603 - Manual (Page 2)

DS1603
2 of 9
With RST at high level 8 bits are loaded into the protocol shift register providing read/write, register
select, register clear, and oscillator trim information. Each bit is serially input on the rising edge of the
clock input. After the first eight clock cycles have loaded the protocol register with a valid protocol
additional clocks will output data for a read or input data for a write. V
CC
must be present to access the
DS1603. If V
CC
< V
TP
, the DS1603 will switch to internal power and disable the serial port to conserve
energy. When running off of the internal power supply, only the continuous counter will continue to
count and the counter powered by V
CC
will stop, but retain the count, which had accumulated when V
CC
power was lost. The 32-bit V
CC
counter is gated by V
CC
and the internal 1Hz signal.
PROTOCOL REGISTER
The protocol bit definition is shown in Figure 2. Valid protocols and the resulting actions are shown in
Table 1. Each data transfer to the protocol register designates what action is to occur. As defined, the
MSB (bit 7 which is designated ACC) selects the 32-bit continuous counter for access. If ACC is a logical
1 the continuous counter is selected and the 32 clock cycles that follow the protocol will either read or
write this counter. If the counter is being read, the contents will be latched into a different register at the
end of protocol and the latched contents will be read out on the next 32 clock cycles. This avoids reading
garbled data if the counter is clocked by the oscillator during a read. Similarly, if the counter is to be
written, the data is buffered in a register and all 32 bits are jammed into the counter simultaneously on the
rising edge of the 32
nd
clock. The next bit (bit 6 which is designated AVC) selects the 32–bit V
CC
active
counter for access. If AVC is a logical 1 this counter is selected and the 32 clock cycles that follow will
either read or write this counter. If both bit 7 and bit 6 are written to a logic high, all clock cycles beyond
the protocol are ignored and bit 5, 4, and 3 are loaded into the oscillator trim register. A value of binary 3
(011) will give a clock accuracy of
±
120 seconds per month at +25
°
C. Increasing the binary number
towards 7 will cause the real- time clock to run faster. Conversely, lowering the binary number towards 0
will cause the clock to run slower. Binary 000 will stop the oscillator completely. This feature can be used
to conserve battery life during storage. In this mode the internal power supply current is reduced to 100
nA maximum. In applications where oscillator trimming is not practical or not needed, a default setting of
011 is recommended. Bit 2 of protocol (designated CCC) is used to clear the continuous counter. When
set to logic 1, the continuous counter will reset to 0 when RST is taken low. Bit 1 of protocol (designated
CVC) is used to clear the V
CC
active counter. When set to logical 1, the V
CC
active counter will reset to 0
when RST is taken low. Both counters can be reset simultaneously by setting CCC and CVC both to a
logical 1. Bit 0 of the protocol (designated RD) determines whether the 32 clocks to follow will write a
counter or read a counter. When RD is set to a logical 0 a write action will follow when RD is set to a
logical 1 a read action will follow. When sending the protocol, 8 bits should always be sent. Sending less
than 8 bits can produce erroneous results. If clearing the counters or trimming the oscillator, the data
transfer can be terminated after the 8-bit protocol is sent. However, when reading or writing the counters,
32 clock cycles should always follow the protocol.
RESET AND CLOCK CONTROL
All data transfers are initiated by driving the RST input high. The RST input has two functions. First,
RST turns on the serial port logic, which allows access to the protocol register for the protocol data entry.
Second, the RST signal provides a method of terminating the protocol transfer or the 32-bit counter
transfer. A clock cycle is a sequence of a rising edge followed by a falling edge. For write inputs, data
must be valid during the rising edge of the clock. Data bits are output on the falling edge of the clock
when data is being read. All data transfers terminate if the RST input is transitioned low and the DQ pin
goes to a high- impedance state. RST should only be transitioned low while the clock is high to avoid
disturbing the last bit of data. All data transfers must consist of 8 bits when transferring protocol only or
8 + 32 bits when reading or writing either counter. Data transfer is illustrated in Figure 3.