Rainbow Electronics BR24L04FVM-W - Manual (Page 6)

BR24L04-W / BR24L04F-W / BR24L04FJ-W
Memory ICs BR24L04FV-W / BR24L04FVM-W
6/25
zSynchronous data timing
t BUF
t PD
t HIGH
t HD : STA t LOW
t F t R
SCL
START BIT STOP BIT
SCL
SDA
t DH
t SU : DAT t HD : DAT
t SU : STO t HD : STA t SU : STA
SDA
(OUT)
SDA
(IN)
Fig.4 SYNCHRONOUS DATA TIMING
•SDA data is latched into the chip at the rising edge of SCL clock.
•Output data toggles at the falling edge of SCL clock.
zWrite cycle timing
ACK D0
t WR
SDA
SCL
START CONDITION STOP CONDITION
WRITE DATA (n)
Fig.5 WRITE CYCLE TIMING