Rainbow Electronics MAX2982 User Manual

Abridged, Max2982 industrial broadband powerline modem, General description

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MAX2982

Industrial Broadband Powerline Modem

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19-5722; Rev 0; 9/11

For related parts and recommended products to use with this part,
refer to

www.maxim-ic.com/MAX2982.related

.

General Description

The MAX2982 powerline transceiver utilizes state-of-the-
art CMOS design techniques to deliver the highest level
of performance, flexibility, and operational temperature
range at reduced cost. This highly integrated design
combines the media access control (MAC) and the phys-
ical (PHY) layers in a single device. The MAX2982 digital
baseband and its companion device, the MAX2981
analog front-end (AFE) with integrated line driver, offer a
complete high-speed powerline communication solution
fully compliant with HomePlug

M

1.0 Powerline Alliance

Specification.
The MAX2982 offers reliable broadband communication
for industrial environments. The PHY layer comprises an
84-carrier OFDM modulation engine and forward error
correcting (FEC) blocks. The OFDM engine can modulate
the signals in one of four modes of operation: DBPSK,
DQPSK (1/2 rate FEC), DQPSK (3/4 rate FEC), and ROBO.
The MAX2982 offers -1dB SNR performance in ROBO
mode, a robust mode of operation, to maintain commu-
nication over harsh industrial line conditions. Additionally,
advanced narrow-band interference rejection circuitry
provides immunity from jammer signals.
The MAX2982 offers extensive flexibility by integrating an
ARM946E-S™ microprocessor allowing feature enhance-
ment, worldwide regulatory compliance, and improved
testability. Optional spectral shaping and notching pro-
files provide an unparalleled level of flexibility in system
design. Additionally, the automatic channel adaptation
and interference rejection features of the MAX2982 guar-
antee outstanding performance. Privacy is provided by a
hard-macro DES encryption with key management.
The MAX2982 supports an IEEE

®

802.3 standard Media

Independent Interface (MII), Reduced Media Independent
Interface (RMII), synchronous FIFO supporting a glue-
free interface to microcontrollers, USB1.1, and 10/100
Ethernet MAC. These interfaces and standards compli-
ance simplify configuration of monitoring and control
networks. Fast response time and an integrated tempera-
ture sensor make the MAX2982 an excellent solution for
real-time control over power lines. The MAX2982 operates
over the -40NC to +105NC temperature range and is avail-
able in a 128-pin, lead-free, LQFP package.

Features

S

Single-Chip Powerline Networking Transceiver

S

HomePlug 1.0 Compliant

S

-40°C to +105°C Operating Temperature Range

S

Integrated Temperature Sensor

S

Up to 14Mbps Data Rate

S

Low-Rate Adaptation (LORA) Operation Option

Provides -2dB SNR Performance at 500kbps

S

4.49MHz to 20.7MHz Frequency Band

S

Flexible MAC/PHY

Field Upgradable Firmware Using TFTP

Spectral Shaping Including Bandwidth and

Notching Capability

Programmable Preamble

128kB Internal SRAM

S

Advanced Narrowband Interference Rejection

Circuitry

S

84-Carrier, OFDM-Based PHY

Automatic Channel Adaptation

FEC (Forward Error Correction)

DQPSK, DBPSK Modulation

Enhanced ROBO Mode with -1dB SNR

S

Large Bridge Table: Up to 512 Addresses

S

56-Bit DES Encryption with Key Management for

Secure Communication

S

On-Chip Communication Interfaces

UART

10/100 Ethernet

MII/RMII

USB1.1

High-Speed Synchronous FIFO

S

AEC-Q100-REV-G Automotive Grade Qualification

Applications

Industrial Automation
Motor Control
Remote Monitoring and Control
Building Automation
Broadband Over Shared Coax/Copper Line

HomePlug is a registered trademark of HomePlug Powerline

Alliance, Inc.
ARM946E-S is a trademark of ARM Limited.
IEEE is a registered service mark of the Institute of Electrical

and Electronics Engineers, Inc.

Ordering Information

appears at end of data sheet.

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

ABRIDGED

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Table of contents

Document Outline

  • General Description
  • Features
  • Applications
  • Typical Application Circuit
  • Absolute Maximum Ratings
  • Package Thermal Characteristics
  • Electrical Characteristics
  • AC Timing Characteristics
  • Typical Operating Characteristics
  • Pin Configuration
  • Pin Description
  • Pin Description by Function
  • Functional Diagram
  • Detailed Description
    • MII/RMII/FIFO Interface
      • MII Interface Signals
    • MII MAC and PHY Connections
      • Transmitting
      • Receiving
      • Reduced Media Independent Interface (RMII)
      • RMII Signal Timing
      • FIFO Interface Signals
      • Transmitting
      • Receiving
      • FIFO Read/Write Timing
    • Management Data Unit (MDU)
    • Ethernet Interface
    • UART Interface
    • USB Interface
  • Applications Information
    • Disabling Ethernet and MII/RMII/FIFO Interface
      • Configure UART I/O as Follows to Disable UART Interface
      • Configure JTAG I/O as Follows to Disable JTAG Interface
    • Interfacing the MAX2982 to the MAX2981 Analog Front-End (AFE)
    • MAC Boot Options
      • GPIO Usage by MAX2982 Firmware
      • Upper-Layer Interface Settings
    • Temperature Sensor
  • Ordering Information
  • Chip Information
  • Package Information
  • Revision History
  • LIST OF FIGURES
    • Figure 1. Ethernet MAC and MAX2982 Connection in MII Mode
    • Figure 2. Receive Defer in MII Mode
    • Figure 3. Transmission Behavior of the MII Interface
    • Figure 4. MII Interface Detailed Transmit Timing
    • Figure 5. Receive Behavior of the MII Interface
    • Figure 6. MII Interface Detailed Receive Timing
    • Figure 7. MAC-PHY Connection in RMII Mode
    • Figure 8. External Host and MAX2982 Connection in FIFO mode
    • Figure 9. Buffering FIFO Transmission Process from External Host
    • Figure 10. Transmission Timing of the Buffering (FIFO) Interface
    • Figure 11. Buffering FIFO Interface Receive Process from the External Host View
    • Figure 12. Receive Timing of Buffering (FIFO) Interface
    • Figure 13. MAX2982 FIFO Read Timing Diagram
    • Figure 14. MAX2982 FIFO Write Timing Diagram
    • Figure 15. Typical Interface Between a Microcontroller and MAX2982
    • Figure 16. Write Behavior of the Management Data Unit
    • Figure 17. Read Behavior of Management Data Unit
    • Figure 18. Transmit Timing for Ethernet MAC Interface
    • Figure 19. Receive Timing for Ethernet MAC Interface
    • Figure 20. MAX2982 UART Interface with Driver and DB9 Connector
    • Figure 21. USB Cable
    • Figure 22. MAX2981 AFE Interface to MAX2982
    • Figure 23. AFE TX Timing Diagram
    • Figure 24. AFE RX Timing Diagram
  • LIST OF TABLES
    • Table 1. Upper Layer Interface Selection GPIO Settings
    • Table 2. MII Signal Description
    • Table 3. MII Interface Detailed Transmit Timing
    • Table 4. MII Interface Detailed Receive Timing
    • Table 5. RMII Signal Description
    • Table 6. FIFO Signal Description
    • Table 7. Upper-Layer Interface Selection GPIO Settings
    • Table 8. UART Interface Configuration
    • Table 9. Upper-Layer Interface Selection GPIO Settings
    • Table 10. MAX2982 to AFE Signal interface
    • Table 11. Boot Modes
    • Table 12. Boot Error Codes
    • Table 13. GPIO Pins Used by MAX2982 Firmware
    • Table 14. Upper-Layer Interface Settings
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