Rainbow Electronics MAX1181 - Manual (Page 5)

MAX1181
Dual 10-Bit, 80Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
_______________________________________________________________________________________ 5
-100
-80
-90
-60
-70
-40
-50
-30
-10
-20
0
0 10 15 5 20 25 30 35 40
FFT PLOT CHA (8192-POINT RECORD,
DIFFERENTIAL INPUT)
MAX1181 toc01
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
f INA = 6.0449MHz
f
INB
= 7.5099MHz
f CLK = 80.000568MHz
AINA = -0.46dB FS
CHA
-100
-80
-90
-60
-70
-40
-50
-30
-10
-20
0
0 10 15 5 20 25 30 35 40
FFT PLOT CHB (8192-POINT RECORD,
DIFFERENTIAL INPUT)
MAX1181 toc02
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
f INA = 6.0449MHz
f
INB
= 7.5099MHz
f CLK = 80.000568MHz
AINB = -0.52dB FS
CHB
-100
-80
-90
-60
-70
-40
-50
-30
-10
-20
0
0 10 15 5 20 25 30 35 40
FFT PLOT CHA (8192-POINT RECORD,
DIFFERENTIAL INPUT)
MAX1181 toc03
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
f INA = 19.9123MHz
f INB = 24.9123MHz
f CLK = 80.000568MHz
AINA = -0.52 dB FS
CHA
Typical Operating Characteristics
(V DD = +3V, OV DD = +2.5V, internal reference, differential input at -0.5dB FS, f CLK = 80.0005678MHz, C L
≈ 10pF. T
A = +25°C,
unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Operating, f
INA or B
= 20MHz at -0.5dB FS 246 291 mW
Sleep mode 8.4 Power Dissipation PDISS
Shutdown, clock idle, PD = OE = OV DD 3 45
µW
Offset ±0.2 mV/V
Power Supply Rejection PSRR
Gain ±0.1 %/V
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid t DO Figure 3 (Note 3) 5 8 ns
Output Enable Time t ENABLE Figure 4 10 ns
Output Disable Time t DISABLE Figure 4 1.5 ns
CLK Pulse Width High t CH Figure 3 clock period: 12ns 6 ±1 ns
CLK Pulse Width Low t
CL
Figure 3 clock period: 12ns 6 ±1 ns
Wakeup from sleep mode (Note 4) 0.28
Wake-Up Time t WAKE
Wakeup from shutdown (Note 4) 1.5
µs
CHANNEL-TO-CHANNEL MATCHING
Crosstalk f INA or B = 20MHz at -0.5dB FS -70 dB
Gain Matching f INA or B = 20MHz at -0.5dB FS 0.02 ±0.2 dB
Phase Matching f INA or B = 20MHz at -0.5dB FS 0.25 degrees
ELECTRICAL CHARACTERISTICS (continued)
(V DD = +3V, OV DD = +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through
a 10k Ω resistor, V
IN = 2V p-p (differential w.r.t. COM), C L = 10pF at digital outputs (Note 5), f CLK = 83.333MHz (50% duty cycle), T A =
T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25°C.)
Note 1: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dB FS, referenced to a +1.024V full-scale
input voltage range.
Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB or better, if referenced to the two-tone envelope.
Note 3: Digital outputs settle to V IH , V IL . Parameter guaranteed by design.
Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
Note 5: Equivalent dynamic performance is obtainable over full OV
DD range with reduced C L .