Rainbow Electronics MAX1209 - Manual (Page 17)

The state of the duty-cycle equalizer input (DCE)
changes the waveform at DAV. With the duty-cycle
equalizer disabled (DCE = low), the DAV signal is the
inverse of the signal at CLKP delayed by 6.8ns. With the
duty-cycle equalizer enabled (DCE = high), the DAV sig-
nal has a fixed pulse width that is independent of CLKP.
In either case, with DCE high or low, output data at
D11–D0 and DOR are valid from 7.7ns before the rising
edge of DAV to 4.2ns after the rising edge of DAV, and
the rising edge of DAV is synchronized to have a 6.4ns
(t
DAV ) delay from the falling edge of CLKP.
DAV is high impedance when the MAX1209 is in
power-down (PD = high). DAV is capable of sinking
and sourcing 600µA and has three times the drive
strength of D11–D0 and DOR. DAV is typically used to
latch the MAX1209 output data into an external back-
end digital circuit.
Keep the capacitive load on DAV as low as possible
(<25pF) to avoid large digital currents feeding back
into the analog portion of the MAX1209 and degrading
its dynamic performance. An external buffer on DAV
isolates it from heavy capacitive loads. Refer to the
MAX1211 evaluation kit schematic for an example of
DAV driving back-end digital circuitry through an exter-
nal buffer.
Data Out-of-Range Indicator (DOR)
The DOR digital output indicates when the analog input
voltage is out of range. When DOR is high, the analog
input is out of range. When DOR is low, the analog
input is within range. The valid differential input range is
from (V
REFP - V REFN ) to (V REFN - V REFP ). Signals out-
side this valid differential range cause DOR to assert
high as shown in
Table 2 and Figure 6.
DOR is synchronized with DAV and transitions along
with the output data D11–D0. There is an 8.5 clock-
cycle latency in the DOR function as with the output
data (
Figure 6).
DOR is high impedance when the MAX1209 is in
power-down (PD = high). DOR enters a high-imped-
ance state within 10ns after the rising edge of PD and
becomes active 10ns after PD’s falling edge.
Digital Output Data (D11–D0), Output Format (G/
T
)
The MAX1209 provides a 12-bit, parallel, tri-state out-
put bus. D11–D0 and DOR update on the falling edge
of DAV and are valid on the rising edge of DAV.
The MAX1209 output data format is either Gray code or
two’s complement, depending on the logic input G/T.
With G/T high, the output data format is Gray code.
With G/T low, the output data format is two’s comple-
ment. See
Figure 8 for a binary-to-Gray and Gray-to-
binary code-conversion example.
The following equations, Table 2, Figure 7, and Figure 8
define the relationship between the digital output and
the analog input:
for Gray code (G/T = 1)
V V V V
CODE
INP INN REFP REFN
( ) − = − Ч Ч
−
2
2048
4096
10
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
______________________________________________________________________________________ 17
DAV
D11–D0
N N+1 N+2
N+3
N+4 N+5
N+6
N+7
N+8
N+9
t DAV
t SETUP
t AD
N-1
N-2
N-3
t HOLD
t CL t CH
DOR
8.5 CLOCK-CYCLE DATA LATENCY
DIFFERENTIAL ANALOG INPUT (INP–INN)
t SETUP t HOLD
N N+1 N+2 N+3 N+5 N+6 N+7 N-1 N-2 N-3 N+9 N+4 N+8
CLKN
CLKP
(V REFP - V REFN )
(V REFN - V REFP )
Figure 6. System Timing Diagram