Rainbow Electronics MAX3805 User Manual
Page 7
frequency components remain essentially intact. These
changes in the spectral characteristic of the signal at
the output of the path are measured with the two power
detectors to provide a means to determine the path
loss.
The dual power-detector feedback loop measures the
ratio between the outputs of the two power detectors
and adjusts the attenuation to restore the sin
2
(f)/f
2
characteristic. The time constant for this feedback loop
is nominally 10µs.
Operating with Different Data Rates and
Codes
The MAX3805 equalizer feedback loop is optimized for
9.95Gbps to 10.7Gbps NRZ PRBS data; however, it
can also be used at a lower data rate or with a different
coding type by adjusting the feedback loop. The rela-
tive gain of the two power detectors can be adjusted by
connecting a 500k
Ω trimmer potentiometer between
HFPD and LFPD pins, with the wiper connected to V
CC
,
as shown in Figure 3. Set the trimmer potentiometer for
the best eye opening.
Adding the potentiometer between HFPD and LFPD
can change the assert and deassert levels of the signal
detector, which could render the signal-detect output
invalid. For normal operation with 9.953Gbps to
10.7Gbps PRBS NRZ data, these signals should be left
open with no connections to pin 13 (HFPD) or pin 14
(LFPD). Note that excessive capacitance on pin 13 or
pin 14 can affect the operation of the feedback loop.
Make certain that the PC board traces from these pins
to the trimmer potentiometer are kept short.
Enable Function
The EN output is an LVCMOS-compatible pin that
enables the output stage of the MAX3805. Connect EN
to V
CC
or LVCMOS high to enable the output stage of
the device or to GND or LVCMOS low to disable the
output stage of the device.
Signal Detect
The output of the high-frequency power detector is
used to generate an LVCMOS-compatible signal-detect
(SD) output. The SD output asserts when the input sig-
nal at the transmission line falls below 200mV
P-P
, and
deasserts when the input signal at the transmission line
rises above 220mV
P-P
. The SD output can be directly
connected to the EN input to disable the MAX3805 out-
put when no data signal is available. The SD output has
an LVCMOS fanout of one.
Package and Layout Considerations
The MAX3805 is packaged in a 3mm x 3mm plastic-
encapsulated 16-lead thin QFN package with exposed
pad for signal integrity. The exposed pad provides ther-
mal and electrical connectivity to the IC, and must be
soldered to a high-frequency ground plane. Use good
layout techniques for the10Gbps SDI and SDO PC
board transmission lines, and configure the trace geom-
etry near the IC package to minimize impedance dis-
continuities. Power-supply decoupling capacitors
should be provided for each supply connection and
located as close as practical to the IC package.
MAX3805
10.7Gbps Adaptive Receive Equalizer
_______________________________________________________________________________________
7
MAX3805
50
Ω
TRANSMISSION LINE
0.01
µF
0.01
µF
V
CC1
50
Ω
IN+
IN-
Figure 2. Single-Ended Operation
V
CC
500k
Ω
LFPD
HFPD
MAX3805
Figure 3. Connecting a Potentionmeter Across HFPD and LFPD
60k
Ω
ESD
STRUCTURES
V
CC
SD
Figure 4. Signal-Detect Output Circuit