Max1510 low-voltage ddr linear regulator, Detailed description, Pin description – Rainbow Electronics MAX1510 User Manual
Page 7
MAX1510
Low-Voltage DDR Linear Regulator
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7
Detailed Description
The MAX1510 is a low-voltage, low-dropout DDR termi-
nation linear regulator with an external bias supply
input and a buffered reference output (see Figures 1
and 2). V
CC
is powered by a 2.7V to 3.6V supply that is
commonly available in laptop and desktop computers.
The 3.3V bias supply drives the gate of the internal
pass transistor, while a lower voltage input at the drain
of the transistor (IN) is regulated to provide V
OUT
. By
using separate bias and power inputs, the MAX1510
can drive an n-channel high-side MOSFET and use a
lower input voltage to provide better efficiency.
The MAX1510 regulates its output voltage to the volt-
age at REFIN. When used in DDR applications as a
termination supply, the MAX1510 delivers 1.25V or
0.9V at 3A peak (typ) from an input voltage of 1.1V to
3.6V. The MAX1510 sinks up to 3A peak (typ) as
required in a termination supply. The MAX1510 pro-
vides shoot-through protection, ensuring that the
source and sink MOSFETs do not conduct at the same
time, yet produces a fast source-to-sink load transient.
OUT
IN
AGND
PGND
V
OUT
= V
TT
= V
DDQ
/ 2
C
IN2
10
µF
C
OUT1
100
µF
C1
1.0
µF
R3
100k
Ω
OFF
V
DDQ
ON
R2
10k
Ω
3.3V BIAS
SUPPLY
V
IN
=
1.1V TO 3.6V
POWER-GOOD
R1
10k
Ω
V
REFOUT
= V
TTR
C
REFOUT
0.33
µF
REFOUT
MAX1510
V
CC
PGOOD
SHDN
REFIN
C
REFIN
1000pF
OUTS
Figure 1. Standard Application Circuit
PIN
NAME
FUNCTION
1
REFOUT
Buffered Reference Output. The output of the unity-gain reference input buffer sources and sinks over
5mA. Bypass REFOUT to AGND with a 0.33µF or greater ceramic capacitor.
2
V
CC
Analog Supply Input. Connect to the system supply voltage (+3.3V). Bypass V
CC
to AGND with a 1µF or
greater ceramic capacitor.
3
AGND
Analog Ground. Connect the backside pad to AGND.
4
REFIN
External Reference Input. REFIN sets the output regulation voltage (V
OUTS
= V
REFIN
).
5
PGOOD
Open-Drain Power-Good Output. PGOOD is low when the output voltage is more than 150mV (typ) above
or below the regulation point, during soft-start, and when shut down. 2ms after the output reaches the
regulation voltage during startup, PGOOD becomes high impedance.
6
OUTS
Output Sense Input. The OUTS regulation level is set by the voltage at REFIN. Connect OUTS to the
remote DDR termination bypass capacitors. OUTS is internally connected to OUT through a 12k
Ω
resistor.
7
SHDN
Shutdown Control Input. Connect to V
CC
for normal operation. Connect to analog ground to shut down the
linear regulator. The reference buffer remains active in shutdown.
8
PGND
Power Ground. Internally connected to the output sink MOSFET.
9
OUT
Output of the Linear Regulator
10
IN
Power Input. Internally connected to the output source MOSFET.
Pin Description