Rainbow Electronics LM95010 - Manual (Page 11)

1.0 Functional Description
(Continued)
• Data Bits This is the data written to the LM95010 regis-
ter, are driven by the master. Data is transferred serially
with the most significant bit first. The number of data bits
may vary from one address to another, based on the size
of the register in the LM95010. This allows throughput
optimization based on the information that needs to be
written.
The LM95010 supports 8-bit or 16-bit data fields, as
described in Section 2.0 "Register Set".
• Even Parity (EP) This data bit is based on all preceding
bits (Device Number, Internal Address, Read/Write and
Data bits) and the Even Parity bit itself. The parity (num-
ber of 1’s) of all the preceding bits and the parity bit must
be even - i.e. the result must be 0. During a write trans-
action, the EP bit is sent by the master to the LM95010 to
allow the LM95010 to check the received data before
using it.
• Acknowledge (ACK) During the write transaction the
ACK bit is sent by the LM95010 indicating to the master
that the EP was received and was found correct, and that
no conflict was detected on the bus (excluding Attention
Request - see Section 1.3.5 "Attention Request Transac-
tion"). A write transfer is considered "completed" only
when the ACK bit is generated. A transaction that was not
positively acknowledged is not considered complete by
the LM95010 (i.e. internal operation related to the trans-
action are not performed) and the following are per-
formed:
— The BER bit in the LM95010 Device Status register is
set;
— The LM95010 generates an Attention Request before,
or together with the Start Bit of the next transaction
A transaction that was not positively acknowledged is
also not considered "complete" by the master (i.e. inter-
nal operations related to the transaction are not per-
formed). The transaction may be repeated by the master,
after detecting the source of the Attention Request (the
LM95010 that has a set BER bit in the Device Status
register). Note that the SensorPath protocol neither
forces, nor automates re-execution of the transaction by
the master.
The values of the ACK bit are:
— 1: Data was received correctly;
— 0: An error was detected (no-acknowledge).
1.3.4 Read and Write Transaction Exceptions
This section describes master and LM95010 handling of
special bus conditions, encountered during either Read or
Write transactions.
If an LM95010 receives a Start Bit in the middle of a trans-
action, it aborts the current transaction (the LM95010 does
not "complete" the current transaction) and begins a new
transaction. Although not recommend for SensorPath normal
operation, this situation is legitimate, therefore it is not
flagged as an error by the LM95010 and Attention Request is
not generated in response to it. The master generating the
Start Bit, is responsible for handling the not "complete" trans-
action at a "higher level".
If LM95010 receives more than the expected number of data
bits (defined by the size of the accessed register), it ignores
the unnecessary bits. In this case, if both master and
LM95010 identify correct EP and ACK bits they "complete"
the transaction. However, in most cases, the additional data
bits differ from the correct EP and ACK bits. In this case, both
the master and the LM95010 do not "complete" the transac-
tion. In addition, the LM95010 performs the following:
• the BER bit in the LM95010 Device Status register is set
• the LM95010 generates an Attention Request
If the LM95010 receives less than the expected number of
data bits (defined by the size of the accessed register), it
waits indefinitely for the missing bits to be sent by the
master. If then the master sends the missing bits, together
with the correct EP/ACK bits, both master and LM95010
"complete" the transaction. However, if the master starts a
new transaction generating a Start Bit, the LM95010 aborts
the current transaction (the LM95010 does not "complete"
the current transaction) and begins the new transaction. The
master is not notified by the LM95010 of the incomplete
transaction.
1.3.5 Attention Request Transaction
Attention Request is generated by the LM95010 when it
needs the attention of the master. The master and all
LM95010s must monitor the Attention Request to allow bit
re-sending in case of simultaneous start with a Data Bit or
Start Bit transfer. Refer to the "Attention Request" section,
Section 1.2.4 in the "Bit Signaling" portion of the data sheet.
The LM95010 will generate an Attention Request using the
following rules:
1. A Function event that sets the Status Flag has occurred
and Attention Request is enabled and
2. The "physical" condition for an Attention Request is met
(i.e., the bus is inactive), and
3. At the first time 2 is met after 1 occurred, there has not
been an Attention request on the bus since a read of the
Device Status register, or since a Bus Reset.
OR
20082010
FIGURE 8. Write Transaction, master write data to LM95010
LM95010
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