Rainbow Electronics MAX3420E - Manual (Page 6)

MAX3420E
mode, these status bits are accessed in the normal
way, as register bits.
The first five registers (R0–R4) access endpoint FIFOs.
To access a FIFO, an initial command byte sets the
register address and then consecutive reads or writes
keep the same register address to access subsequent
FIFO bytes.
The remaining registers (R5–R20) control the operation
of the MAX3420E. Once a register address above R4 is
set in the command byte, successive byte reads or
writes in the same SPI access cycle (
SS low) increment
the register address after every byte read or written. This
incrementing operation continues until R20 is accessed.
Subsequent byte reads or writes continue to access
R20. Note that this auto-incrementing action stops with
the next SPI cycle, which establishes a new register
address. Addressing beyond R20 is ignored.
USB Peripheral Controller
with SPI Interface
6 _______________________________________________________________________________________
Table 1. MAX3420E Register Map
R EG NAME b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 a c c
R0 EP0 F IF O b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 RS C
R1 EP1 O U T F IF O b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 RS C
R2 EP2 IN F IF O b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 RS C
R3 EP3 IN F IF O b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 RS C
R4 SU D F IF O b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 RS C
R5 EP0 B C 0 b 6 b 5 b 4 b 3 b 2 b 1 b 0 RS C
R6 EP1 O U T B C 0 b 6 b 5 b 4 b 3 b 2 b 1 b 0 RS C
R7 EP2 IN B C 0 b 6 b 5 b 4 b 3 b 2 b 1 b 0 RS C
R8 EP3 IN B C 0 b 6 b 5 b 4 b 3 b 2 b 1 b 0 RS C
R9 EPST A L L S 0 AC KS TAT S TLS TAT S TLE P 3IN S TLE P 2IN S TLE P 1OU T S TLE P 0OU T S TLE P 0IN RS C
R10 C L R T O G S E P 3D IS AB E P 2D IS AB E P 1D IS AB C TG E P 3IN C TG E P 2IN C TG E P 1OU T 0 0 RS C
R11 EPI R Q 0 0 S U D AV IRQ IN 3BAV IRQ IN 2BAV IRQ OU T1D AV IRQ OU T0D AV IRQ IN 0BAV IRQ RC
R12 EPI EN 0 0 S U D AV IE IN 3BAV IE IN 2BAV IE OU T1D AV IE OU T0D AV IE IN 0BAV IE RS C
R13 U SB IR Q U RE S D N IRQ V BU S IRQ N OV BU S IRQ S U S P IRQ U RE S IRQ BU S AC TIRQ RWU D N IRQ OS C OKIRQ RC
R14 U SB IEN U RE S D N IE V BU S IE N OV BU S IE S U S P IE U RE S IE BU S AC TIE RWU D N IE OS C OKIE RS C
R15 U SB C T L H OS C S TE N V BG ATE C H IP RE S P WRD OWN C ON N E C T S IG RWU 0 0 RS C
R16 C PU C T L 0 0 0 0 0 0 0 IE RS C
R17 PIN C T L E P 3IN AK E P 2IN AK E P 0IN AK FD U P S P I IN TLE V E L P OS IN T GP X B GP X A RS C
R18 R EVISIO N 0 0 0 0 0 0 1 0 R
R19 F N A D D R 0 b 6 b 5 b 4 b 3 b 2 b 1 b 0 R
R20 IO PIN S GP IN 3 GP IN 2 GP IN 1 GP IN 0 GP O U T3 GP O U T2 GP O U T1 GP O U T0 RS C
Note: The acc (access) column indicates how the SPI Master can access the register.
R = Read, RC = Read or Clear, RSC = Read, Set, or Clear.
Writing to an R register (Read-Only) has no effect.
Writing a 1 to an RC bit (Read or Clear) clears the bit.
Writing a zero to an RC bit has no effect.