Ocean Optics EMBED2000+ - Manual (Page 9)

EMBED2000+ Data Sheet
029-20000-005-05-201305 9
FPGA_OFFSETVALUE -0x5C
This register is a calibration value for consistent detector baselines.
FPGA_MAXSATVALUE -0x68
This register is a calibration value for scaling to 16-bit.
Data for both register addresses 0x5C and 0x68 are obtained from the SPI calibration EEPROM. This
value is static and needs to be written only once following an X_RESET event.
Spectral Acquisition
The following diagram shows the two possible sources for triggering an acquisition: FIFO_RESET or
Trigger. Both are identical in functionality.
FIFO_RESET or Trigger
PIXEL_RDY
Trigger Mode
Integration time (note1)
Note 1: The FPGA has a set up time of 840ns from the time the acquisition source goes high to when
the ILX511B begins integrating.
When the integration time has expired and the first pixel is available in memory, PIXEL_RDY will
assert high and contents are ready to be read as described in “Reading Pixel Data”
Reading Pixel Data
The following diagram shows how to receive spectral data over SPI. PIXEL_RDY is reported by the
FPGA once an unread pixel is ready in the FIFO. To read the FIFO contents FIFO_CS is brought low
to shift FIFO data to an internal buffer awaiting SPI transfer.
This process is repeated for the entire 2048 pixel FIFO, however it is not required to read out all 2048
pixels. The read process can be aborted and a new scan initiated by issuing a FIFO_RESET or
External Trigger.
PIXEL_RDY
FIFO_CS
MISO
SPI_CLK
6 5 15 14 13 12 11 4 3 2 1 0
nth Pixel Read Example
10 9 8 7