SP / Silicon Power SP001GBRDE333O01 - Manual

SP001GBRDE333O01
184pin DDR 333 Registered DIMM
This document is a general product description and is subject to change without notice
1. Description
The SP001GBRDE333O01 is a 64M x 8bits Double Data Rate SDRAM high-density for
DDR-333.The SP001GBRDE333O01 consists of 16pcs CMOS 64x8 bits Double Data Rate
SDRAMs in 66 pin TSOP package, and a 2048 bits serial EEPROM on a 184-pin printed
circuit board. The SP001GBRDE333O01 is a Dual In-Line Memory Module and is intended
for mounting into 184-pin connector sockets. Synchronous design allows precise cycle
control with the use of system clock. Data I/O transactions are possible on both edges of
DQS. Range of operation frequencies, programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance memory system applications.
2. Features
․Double--data--rate architecture; two data transfers per clock cycle
․Bidirectional, data strobe (DQS) is transmitted/received with data, to be used in capturing
data at the receiver
․DQS is edge--aligned with data for READs; center--aligned with data for WRITEs
․Differential clock inputs (CK and /CK)
․DLL aligns DQ and DQS transitions with CK transitions
․Commands entered on each positive CK edge; data and data mask referenced to both
edges of DQS
․Four internal banks for concurrent operation
․Registered inputs with one-clock delay
․Phase-lock loop (PLL) clock driver to reduce loading
․Supports ECC error detection and correction
․Data mask (DM) for write data
․Burst lengths: 2, 4, or 8
․AUTOPRECHARGE option for each burst access
․Auto Refresh and Self Refresh Modes
․JEDEC standard 2.5 V (SSTL_2 compatible) I/O
․66pin TSOP II Leaded & Pb-Free (RoHS compliant) package