12 security block register descriptions, Security block register descriptions, Table 6-78 – AMD Geode LX [email protected] User Manual

Page 513: Standard geodelink™ device msrs summary, Table 6-79, Security block specific msrs, Table 6-80

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AMD Geode™ LX Processors Data Book

513

Security Block Register Descriptions

33234H

6.12

Security Block Register Descriptions

This section provides information on the registers associ-
ated with the Security Block (SB), including the Standard
GeodeLink Device (GLD) MSRs, the Security Block Spe-
cific MSRs (accessed via the RDMSR and WRMSR
instructions), and the Security Block Configuration/Control reg-
isters. Table 6-78 through Table 6-80 are register summary

tables that include reset values and page references where
the bit descriptions are provided.

The MSR address is derived from the perspective of the
CPU Core. See Section 4.1 "MSR Set" on page 45 for
more detail on MSR addressing.

Table 6-78. Standard GeodeLink™ Device MSRs Summary

MSR Address

Type

Register Name

Reset Value

Reference

58002000h

RO

GLD Capabilities MSR (GLD_MSR_CAP)

00000000_001304xxh

Page 515

58002001h

R/W

GLD Master Configuration MSR
(GLD_MSR_CONFIG)

00000000_00000000h

Page 515

58002002h

R/W

GLD SMI MSR (GLD_MSR_SMI)

00000000_00000007h

Page 516

58002003h

R/W

GLD Error MSR (GLD_MSR_ERROR)

00000000_00000019h

Page 516

58002004h

R/W

GLD Power Management MSR
(GLD_MSR_PM)

00000000_00000015h

Page 518

58002005h

R/W

GLD Diagnostic MSR (GLD_MSR_DIAG)

00000000_00000000h

Page 518

Table 6-79. Security Block Specific MSRs

MSR Address

Type

Register Name

Reset Value

Reference

58002006h

R/W

GLD Control MSR (GLD_MSR_CTRL)

00000000_00000003h

Page 519

Table 6-80. Security Block Configuration/Control Registers Summary

SB Memory

Offset

Type

Register Name

Reset Value

Reference

000h

R/W

SB Control A (SB_CTL_A)

00000000h

Page 520

004h

R/W

SB Control B (SB_CTL_B)

00000000h

Page 521

008h

R/W

SB AES Interrupt (SB_AES_INT)

00000007h

Page 522

010h

R/W

SB Source A (SB_SOURCE_A)

00000000h

Page 522

014h

R/W

SB Destination A (SB_DEST_A)

00000000h

Page 523

018h

R/W

SB Length A (SB_LENGTH_A)

00000000h

Page 523

020h

R/W

SB Source B (SB_SOURCE_B)

00000000h

Page 524

024h

R/W

SB Destination B (SB_DEST_B)

00000000h

Page 524

028h

R/W

SB Length B (SB_LENGTH_B)

00000000h

Page 525

030h

WO

SB Writable Key 0 (SB_WKEY_0)

00000000h

Page 525

034h

WO

SB Writable Key 1 (SB_WKEY_1)

00000000h

Page 526

038h

WO

SB Writable Key 2 (SB_WKEY_2)

00000000h

Page 526

03Ch

WO

SB Writable Key 3 (SB_WKEY_3)

00000000h

Page 527

040h

R/W

SB CBC Initialization Vector 0
(SB_CBC_IV_0)

00000000h

Page 527

044h

R/W

SB CBC Initialization Vector 1
(SB_CBC_IV_1)

00000000h

Page 528

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