AMD Geode LX 800@0.9W - Manual (Page 552)

552 AMD Geode™ LX Processors Data Book
GeodeLink™ Control Processor Register Descriptions 33234H
6.14.2.10 GLCP Clock Active (GLCP_CLKACTIVE)
See "GLCP_CLKOFF Bit Descriptions" on page 551 for bit descriptions.
11 DCDOT_0 DC Dot Clock Off. When set, disables DC Dot Clock 0 (DC).
10 GLIU0_1 GLIU0Clock Off. When set, disables main clock to primary GLIU.
9 GLIU0_0 GLIU0 Timer Logic Clock Off. When set, disables clock to timer logic of primary
GLIU.
8 GP GP Clock Off. When set, disables GP clock (GLIU).
7 GLMC GLMC Clock Off. When set, disables GLIU clock to memory controller.
6 DRAM DRAM Clocks Off. When set, disables external DRAM clocks (and, hence, feedback
clocks).
5 BC_GLIU Bus Controller Clock Off. When set, disables clock to CPU bus controller block.
4 BC_VA CPU to Bus Controller Clock Off. When set, disables CPU clock to bus controller
block.
3 MSS CPU to MSS Clock Off. When set, disables CPU clock to MSS block.
2 IPIPE CPU to IPIPE Clock Off. When set, disable CPU clock to IPIPE block.
1 FPUFAST FPU Fast Clock Off. When set, disables the fast FPU clock.
0 FPUSLOW FPU Clock Off. When set, disables the slow CPU clock to FPU.
MSR Address 4C000011h
Type RO
Reset Value Input Determined
GLCP_CLKOFF Bit Descriptions (Continued)
Bit Name Description
GLCP_CLKACTIVE Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
VIPVIP
VIPGLIU
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES
AESGLIU
AESEE
GLCPDB
G
GLCPGLIU
G
L
CPPCI
VPV
O
P
VPDO
T
_2
VPDO
T
_1
VPDO
T
_0
VPG
LIU
_
1
VPG
LIU
_
0
PCI
P
C
IF
PCIPCI
PCIG
L
IU
GLIU
1_1
GLIU
1_0
DC
GL
IU
_
1
DC
GL
IU
_
0
RSVD
DCD
O
T
_0
GLIU
0_1
GLIU
0_0
GP
GL
M
C
DR
A
M
BC_GLIU
BC_V
A
MSS IPIPE
FPU
F
AST
FPUSLO
W