AMD Geode LX 800@0.9W - Manual (Page 93)

AMD Geode™ LX Processors Data Book 93
CPU Core 33234H
5.3.4 EFLAGS Register
The EFLAGS register contains status information and con-
trols certain operations on the Geode LX processor. The
lower 16 bits of this register are used when executing 8086
or 80286 code. Table 5-4 gives the bit formats for the
EFLAGS register.
Table 5-4. EFLAGS Register
Bit Name Flag Type Description
31:22 RSVD -- Reserved. Set to 0.
21 ID System Identification Bit. The ability to set and clear this bit indicates that the CPUID instruction is sup-
ported. The ID can be modified only if the CPUID bit in CCR4 (Index E8h[7]) is set.
20:19 RSVD -- Reserved. Set to 0.
18 AC System Alignment Check Enable. In conjunction with the AM flag (bit 18) in CR0, the AC flag deter-
mines whether or not misaligned accesses to memory cause a fault. If AC is set, alignment
faults are enabled.
17 VM System Virtual 8086 Mode. If set while in protected mode, the processor switches to virtual 8086 oper-
ation handling segment loads as the 8086 does, but generating exception 13 faults on privileged
opcodes. The VM bit can be set by the IRET instruction (if current privilege level is 0) or by task
switches at any privilege level.
16 RF Debug Resume Flag. Used in conjunction with debug register breakpoints. RF is checked at instruction
boundaries before breakpoint exception processing. If set, any debug fault is ignored on the next
instruction.
15 RSVD -- Reserved. Set to 0.
14 NT System Nested Task. While executing in protected mode, NT indicates that the execution of the current
task is nested within another task.
13:12 IOPL System I/O Privilege Level. While executing in protected mode, IOPL indicates the maximum current
privilege level (CPL) permitted to execute I/O instructions without generating an exception 13
fault or consulting the I/O permission bit map. IOPL also indicates the maximum CPL allowing
alteration of the IF bit when new values are popped into the EFLAGS register.
11 OF Arithmetic Overflow Flag. Set if the operation resulted in a carry or borrow into the sign bit of the result but
did not result in a carry or borrow out of the high-order bit. Also set if the operation resulted in a
carry or borrow out of the high-order bit but did not result in a carry or borrow into the sign bit of
the result.
10 DF Control Direction Flag. When cleared, DF causes string instructions to auto-increment (default) the
appropriate index registers (ESI and/or EDI). Setting DF causes auto-decrement of the index
registers to occur.
9 IF System Interrupt Enable Flag. When set, maskable interrupts (INTR input pin) are acknowledged and
serviced by the CPU.
8 TF Debug Trap Enable Flag. Once set, a single-step interrupt occurs after the next instruction completes
execution. TF is cleared by the single-step interrupt.
7 SF Arithmetic Sign Flag. Set equal to high-order bit of result (0 indicates positive, 1 indicates negative).
6 ZF Arithmetic Zero Flag. Set if result is zero; cleared otherwise.
5 RSVD -- Reserved. Set to 0.
4 AF Arithmetic Auxiliary Carry Flag. Set when a carry out of (addition) or borrow into (subtraction) bit position
3 of the result occurs; cleared otherwise.
3 RSVD -- Reserved. Set to 0.
2 PF Arithmetic Parity Flag. Set when the low-order 8 bits of the result contain an even number of ones; other-
wise PF is cleared.
1 RSVD Reserved. Set to 1.
0 CF Arithmetic Carry Flag. Set when a carry out of (addition) or borrow into (subtraction) the most significant
bit of the result occurs; cleared otherwise.