Teledyne LeCroy PCI Express 2.0 Mid-Bus Probe Ver.2.40 - Manual (Page 15)

Teledyne LeCroy PCIe 2.0 Mid-Bus Probe Installation Guide Version 2.4
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4 Electrical Design
4.1 Probe Loading Effect
The logical probing of the PCI Express bus is achieved by tapping a small amount of energy from the
probed signals and channeling this energy to the analyzer. In order to avoid excessive loading
conditions, the Teledyne LeCroy mid-bus probe employs high impedance tip resistors (isolation resistors).
The probe isolation resistance is selected to both satisfy the probe sensitivity and system parasitic load
requirements.
Extensive care has been taken to reduce the parasitic effect of the probed signals during each phase of
the mid-bus probe design. The figure below shows the equivalent load model of the Mid-bus probe. An
equivalent Spice model is available via the Teledyne LeCroy Protocol Systems Group support team
([email protected])
With this unique design, the Teledyne LeCroy mid-bus probes can capture bus traffic signals with
amplitudes specified by the PCI Express standard, while introducing only the loss and added jitter that are
within the recommended specification in the PCI Express Mid-Bus Probing Footprint and Pinout.
4.2 Overview of Probe - Pin Assignments
Cross-references from the PCI Express Mid-Bus Probing Footprint and Pinout (8/05/03) Revision 1.0 are
given in tables listed below.
Some PCI Express analyzers from Teledyne LeCroy (e.g., the Summit T2-16 and Summit T3-16) support
a lane swizzling feature which allows pairs of differential pin assignments to be re-wired dynamically to
match the configuration under the probe. This also provides additional versatility in the case where two
busses are mapped to the probe footprint and cannot be uniquely positioned within a quadrant. Lane
swizzling allow you to reorder upstream lanes or recorder downstream lanes regardless of the order of
physical connections – however, you cannot interchange upstream lanes with downstream lanes