Teledyne LeCroy TA700_800_850 User Manual - Manual (Page 174)

Catalyst Enterprises, Inc. Special Setups
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ERR21 The target must deasserts TRDY, STOP and DEVSEL on the first clock after the last data phase. PCI-X Rev 1.0 -
1.10.3
ERR22 If the target signals Split Response, Target-Abort, or Retry, the target must do so within 8 clocks of the assertion of
FRAME. PCI-X Rev 1.0 -1.10.3
ERR23 If the target signals Single Data Phase Disconnect, Data Transfer, or Disconnect at Next ADB, the target must do
so within 16 clocks of the assertion of FRAME. PCI-X Rev 1.0 -1.10.3
ERR24 Once the target has signaled Disconnect at Next ADB, it must continue to do so until the end of the transaction or
must signal Target Abort. PCI-X Rev 1.0 -1.10.3
ERR25 The requester must terminate a Split Completion with Data Transfer or Target-Abort (except PCI-X bridge that is
forwarding a Split Completion from one PCI bus to another). PCI-X Rev 1.0 -1.10.8
ERR26 TRDY must be asserted more than one clock after the attribute phase. PCI-X Rev 1.0 -2.8
ERR27 If a transaction has four or more data phases, the initiator signals the end of the transaction by deasserting FRAME
one clock before the last data phase. PCI-X Rev 1.0 -2.11.1.1
ERR28 The initiator must deassert FRAME at least two clocks after the target asserts TRDY. PCI-X Rev 1.0 -2.11.1.1
ERR29 The initiator must deassert IRDY one clock after the last data phase but never less than two clocks after the first
data phase. PCI-X Rev 1.0 -2.11.1.1
ERR30 Not a valid termination with respect to IRDY, FRAME. PCI-X Rev 1.0 -2.11.1.1
ERR31 (*Not implemented*) If the target signals Disconnect at Next ADB less than four data phases from an ADB the
transaction must cross that ADB and disconnects on the next one. PCI-X Rev 1.0 -2.11.2.2
ERR32 Single Data Phase Disconnect, Retry or Split Response must be signaled in the first data phase. PCI-X Rev 1.0 -
2.11.2
ERR33 Master can not insert wait states. PCI-X Rev 1.0 -1.6
ERR34 Target can not insert wait states after first data phase. PCI-X Rev 1.0 -1.6
ERR35 Target initial wait states for memory write and Split Completion transactions must come in pairs. PCI-X Rev 1.0 -
1.6
ERR36 REQ64 can be asserted only for memory transactions (except Memory Read DWORD) or Split Completion. PCI-
X Rev 1.0 -1.10.1
ERR37 (*Not implemented*) Dual transactions should not be used for addresses less that 4GB
ERR38 (*Not implemented *) Dual address & split
ERR39 The first transaction on the LOCK# was not a read transaction. PCI-X Rev 1.0 - 8.5.1
ERR40 LOCK# was not released when Retry was requested by the Target. PCI-X Rev 1.0 - 8.5.1
ERR41 LOCK# was not released after target abort. PCI-X Rev 1.0 - 8.5.1
ERR42 LOCK# was not asserted the clock following the address phase or was not kept asserted throughout the
transaction. PCI-X Rev 1.0 - 8.5.1
ERR43 Target has not recognized configuration cycle type 00 or 01 and has asserted DEVSEL#. PCI-X Rev 1.0 - 1.10.5
Table 4. PCI-X Protocol Errors (0-58)
Err. # Description