IEI Integration SPXE-9S v1.00 - Manual

1
SPXE-9S-R10
9-Slot PICMG 1.3 PCIe Backplane
User Manual Ver. 1.0
1. J1:
PCI-X_A1 Frequency Setting
J2: PCI-X_B1 Frequency Setting
Freq. \ Pin 1 - 2 3 - 4
66MHz Don’t Care Short
100MHz Short Open
133MHz (Default) Open Open
2. J3 & J4: Intel Bridge 41210 SM-BUS Setting
Pin DESCRIPTION
1-2
Normal Operation
(default)
2-3 Test Purposes
3. J5: Intel Bridge 41210 Initialization Register Setting
J5 DESCRIPTION
Open (High) Initialization Register
Short (Low)
Normal response
(default)
4. J6: Intel Bridge 41210 Use MCU read/write Pin
Pin DESCRIPTION
1 MCLR
2 +5V
3 GND
4 RB7/PGD
5 RB6/PGC
Dec. 17, 2007