Abit IL-90MV - Manual (Page 37)

BIOS Setup
iL-90MV 3-9
3.3 Advanced Chipset Features
Phoenix – AwardBIOS CMOS Setup Utility
Advanced Chipset Features
DRAM Timing Selectable By SPD Item Help
X - CAS Latency Time (tCL) Auto
X - RAS# to CAS# Delay (tRCD) Auto
X - RAS# Precharge (tRP) Auto
X - Precharge Delay (tRAS) Auto
X - System Memory Frequency Auto
► PCI Express Root Port Func Press Enter
Init Display First PCI Slot
HDMI Port Display DVI
** VGA Setting **
Frame Buffer Size 8MB
DVMT Mode DVMT
DVMT/FIXED Memory Size 128MB
:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
DRAM Timing Selectable
This item sets the optimal timings for the following four items, depending on the memory
module you are using. The default setting “By SPD” configures these four items by reading the
contents in the SPD (Serial Presence Detect) device. The EEPROM on the memory module
stores critical parameter information about the module, such as memory type, size, speed,
voltage interface, and module banks.
- CAS Latency Time (tCL)
This item controls the latency between the DRAM read command and the time that the data
becomes actually available.
- RAS# to CAS# Delay (tRCD)
This item controls the latency between the DRAM active command and the read/write
command.
- RAS# Precharge (tRP)
This item controls the idle clocks after issuing a precharge command to the DRAM.
- Precharge Delay (tRAS)
This item controls the number of DRAM clocks used for the DRAM parameters.
- System Memory Frequency
This item selects the DRAM speed.