Analog Devices ADSP-2181 User Manual
Page 25
ADSP-2181/ADSP-2183
REV. 0
–25–
ADSP-2181/ADSP-2183
Parameter
Min
Max
Unit
Serial Ports
Timing Requirements:
t
SCK
SCLK Period
50
ns
t
SCS
DR/TFS/RFS Setup before SCLK Low
4
ns
t
SCH
DR/TFS/RFS Hold after SCLK Low
7
ns
t
SCP
SCLK
IN
Width
20
ns
Switching Characteristics:
t
CC
CLKOUT High to SCLK
OUT
0.25t
CK
0.25t
CK
+ 10
ns
t
SCDE
SCLK High to DT Enable
0
ns
t
SCDV
SCLK High to DT Valid
15
ns
t
RH
TFS/RFS
OUT
Hold after SCLK High
0
ns
t
RD
TFS/RFS
OUT
Delay from SCLK High
15
ns
t
SCDH
DT Hold after SCLK High
0
ns
t
TDE
TFS (Alt) to DT Enable
0
ns
t
TDV
TFS (Alt) to DT Valid
14
ns
t
SCDD
SCLK High to DT Disable
15
ns
t
RDV
RFS
(Multichannel, Frame Delay Zero) to DT Valid
15
ns
CLKOUT
SCLK
TFS
RFS
DT
ALTERNATE
FRAME MODE
t
CC
t
CC
t
SCS
t
SCH
t
RH
t
SCDE
t
SCDH
t
SCDD
t
TDE
t
RDV
MULTICHANNEL MODE,
FRAME DELAY 0
(MFD = 0)
DR
TFS
IN
RFS
IN
RFS
OUT
TFS
OUT
t
TDV
t
SCDV
t
RD
t
SCP
t
SCK
t
SCP
Figure 27. Serial Ports