Bios setup – Asus TUA266 User Manual

Page 61

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ASUS TUA266 User’s Manual

61

4. BIOS SETUP

4. BIOS SETUP

SDRAM Cycle Time tRAS [7T]

This feature controls the number of SDRAM clocks used for SDRAM
parameter tRAS. tRAS specifies the minimum clocks required between
active command and precharge command. NOTE: To make changes to
this field, set the SDRAM Configuration field to [User Defined].

MA Offset [0]

Configuration options: [-2] [-1] [0] [1] [2]

System Acceleration Mode [Enabled]

Configuration options: [Disabled] [Enabled]

Graphics Aperture Size [128MB]

This feature allows you to select the size of mapped memory for AGP graphic
data. Configuration options: [1MB] [4MB] [8MB] [16MB] [32MB] [64MB]
[128MB] [256MB]

AGP Capability [4X Mode]

This motherboard supports the AGP 4x interface that transfers video data at
1066MB/s. AGP 4x is backward-compatible, so you may leave the default
[4X Mode] on even if you are using an AGP 1x or 2x video card. When set
to [1X Mode], the AGP interface only provides a peak data throughput of
266MB/s even if you are using an AGP 2x/4x card. When set to [2X Mode],
the AGP interface only provides a peak data throughput of 533MB/s even if
you are using an AGP 4x card. Configuration options: [1X Mode] [2X Mode]
[4X Mode]

Video Memory Cache Mode [UC]

USWC (uncacheable, speculative write combining) is a new cache
technology for the video memory of the processor. It can greatly improve
the display speed by caching the display data. You must set this to UC
(uncacheable) if your display card does not support this feature, otherwise
the system may not boot. Configuration options: [UC] [USWC]

Memory Hole At 15M-16M [Disabled]

This field allows you to reserve an address space for ISA expansion cards.
Setting the address space to a particular setting makes that memory space
unavailable to other system components. Expansion cards can only access
memory up to 16MB. Configuration options: [Disabled] [Enabled]

PCI 2.1 Latency Compliant [Disabled]

This field allows you to enable or disable the PCI 2.1 latency compliant
mode for the primary bus. Configuration options: [Disabled] [Enabled]

Chip Configuration

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