Campbell Scientific SDM-CD16S 16-Channel Solid State DC Relay Controller Module - Manual (Page 13)

SDM-CD16S 16 Channel Solid State DC Control Module
Instruction 29 – SDM-CD16S used with older CR7s
Parameter Type Description
1
2 Reps (No. of modules sequentially addressed)
2 2 Device (2 = SDM-CD16S)
3 2 Starting Address (base 4: 00..33)
4 2 Card (Excitation card No.)
5 4 Starting Input Location
Execution Time = 150ms to 190ms per Rep
The number of SDM-CD16Ss to be addressed is defined by the Reps
(repetitions) parameter. Each Rep sequentially addresses (00, 01, 02,...32, 33)
SDM-CD16Ss, starting with the address specified in parameter 2 (parameter 3
for Instruction 29).
For each repetition, the 16 ports of the addressed SDM-CD16S are set
according to 16 sequential input locations starting at the input location
specified in parameter 3 (parameter 5 for Instruction 29). Any non-zero value
stored in an input location activates (sets HI 5V) the associated SDM-CD16S
port. A value of zero (0) de-activates the port (sets LO 0V). For example,
assuming two repetitions and a starting input location of 33, outputs 1 to 16 of
the first SDM-CD16S are set according to input locations 33 to 48, and outputs
1 to 16 of the second SDM-CD16S are set according to input locations 49 to
64.
For older CR7s with Instruction 29, the Device (parameter 2) specifies what
type of synchronously addressed peripheral is to be addressed. The Device
code for an SDM-CD16S is 2.
For Instruction 29 only (older CR7s), the Card parameter (parameter 4)
specifies which 725 Excitation Card is being used for the control port signals.
The Reps parameter does not advance beyond the specified Card, requiring
another Instruction 29 for each 725 Excitation Card used.
7. Theory of Operation
The SDM-CD16S is a synchronously addressed peripheral. C2 and C3, driven
high by the datalogger, initiate a cycle. While holding C3 high, the datalogger
drives C2 as a clock line and C1 as a serial data line. The datalogger shifts out
a data bit on C1 (LSB first) on the falling edge of the C2 clock. The SDM-
CD16S shifts in the C1 data bit on the rising edge of the C2 clock.
The first 8 bits clocked out represent the SDM-CD16S address. If the address
matches the SDM-CD16S's address, the SDM-CD16S is enabled. If enabled,
the next 16 bits are shifted into the SDM-CD16S, each bit controlling one port,
the first of which controls OUT 1.
When the 16 control bits are clocked in, C2 is held high while C3 is pulsed low
then high to latch the control bits. The datalogger then lowers both C3 and C2
to complete the cycle.
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