Analog Devices HSC-ADC-EVALC - Manual (Page 24)

HSC-ADC-EVALC
Rev. 0 | Page 24 of 32
I/O CONNECTOR—J1, J2, AND J3 PIN MAPPING
D C B A
D C B A
D C B A
D17
A
–
D
16A–
D
14
A
–
D12A–
D
10A
–
D
8A–
D
6A–
D
4A–
D
2A–
D
0A–
D17A+
D
16
A
+
D14A+
D
12A+
D
10A
+
D
8A+
D
6A+
D
4A+
D
2
A
+
D
0
A
+
DC
L
KA1
–
D15A–
D
13
A
–
D11A–
D
9A–
D
7A–
D
5A–
D
3A–
D
1A–
DC
LK
A2
–
DCL
K
A1
+
D15
A
+
D
13A+
D
11A+
D
9
A
+
D
7A+
D
5A+
D
3A+
D
1
A
+
DC
LK
A2+
L
V
DS
DA
T
A P
A
T
H >
CM
O
S
/L
V
D
S
DAT
A P
AT
H >
L
V
DS
DA
T
A P
A
T
H >
CM
O
S
/L
V
D
S
DAT
A P
AT
H >
D17
B
–
D
16B–
D
1
4
B–
D12B–
D
10B–
D
8B–
D
6B–
D
4B–
D
2B–
D
0B–
D17B+
D
16
B
+
D14B+
D
12B+
D
10B+
D
8B+
D
6B+
D
4
B
+
D
2
B
+
D
0
B
+
DC
L
KB1
–
D15B–
D
1
3
B–
D11
B
–
D
9B–
D
7B–
D
5B–
D
3B–
D
1B–
DC
LK
B2
–
DCL
K
B1
+
D15
B
+
D
13B+
D
11B+
D
9
B
+
D
7B+
D
5B+
D
3
B
+
D
1
B
+
DC
LK
B2+
(J
2
) DAT
A BUS 1
(J
3
) DAT
A BUS 2
0667 6-02 1
Figure 21. J2 and J3 Pin Mapping