ALESIS HR-16 - Manual (Page 12)

HR-16/HR16B Service Manual 1.00 6
5.0 Analog Signal Paths
5.1 Drum Signal Output
The output of the DM3AG ASIC is an 18 bit value. This may seem a little strange at first,
since we are using a 16 bit DAC. R63 and R73-R75 provide the binary weighted resistor network
necessary to achieve a full 18 bit output.
The PCM-54 DAC adjust circuit consists of R52, R53, R54, C34, and trimpot R90 (see
section 6.3 regarding adjustment).
The output of the DAC is sent via R68 to the 4052 analog switch (U19), where the ASIC
controls to which output (out1 left/right or out2 left/right) the final signal will be sent. (Note that
stereo panning is achieved by sending the same signal to the left and right sides separately.)
Each output section (consisting of 1/4 of U20, 1/4 of U21, and misc. resistors and capacitors)
serves the dual purposes of filtering and buffering (with a little gain added in). In the case of output
1, the signal is fed through the volume slider (via J11)(see section 7.19 regarding differences in
wiring) before final output to the 1/4 inch jacks.
5.2 Piezo/Data Slider Input
Successive approximation is the method used to determine the value of the keypad piezo
crystals (keypad velocity), and the data slider. It is a heuristic approach to the process of analog to
digital conversion. The idea is to divide the process into short, manageable sections. Each
significant binary weight (starting with the Most Significant Bit) is taken in turn, thus requiring only 8
comparisons to achieve a final value.
74HC04s U2 and U3 (replaced by a single 74HC540 [U2] in revision AQ PC boards) combine
with the binary weighted resistor network (R16-R20, and SIP R22) to form a simple 8 bit digital to
analog converter. The 8031 sends values to the DAC via it's internal I/O ports. The analog
equivalent of these values is compared to the actual input signals via comparators U1 (pins 2, 4,
and 5 for the data slider) and U1 (pins 8, 9, and 14 for the piezos). The 8031 reads the result of the
comparison through I/O port P3.4 (pin 14) or port P3.5 (pin 15) and proceeds according to that
result. The data slider is read directly via R23 (with C16 acting as a filter to reduce "jitter"). However
the piezos require a little bit of wave shaping and translation before they can be read. First, the
signal is A.C. coupled by C50, and rectified by D19. Q3 is then used to translate the signal into a 0V
to 5V range (the piezos can produce up to about 50V). The signal is now ready for conversion.
5.3 Tape I/O
Tape output is very simple, while tape input is somewhat more complicated. This is due to
the fact that tape backup and tape sync have different requirements. Data transfers need data
integrity which implies guaranteed highs and lows, while tape sync needs tight timing and fast
transistions. It's important to remember that not all tape decks are created equal. Probably the
largest factor involved is the decks input and output capacitances. These can greatly affect the
signals sent to and from the deck, and may cause some decks to be incompatible with the tape I/O
needs of the HR-16. However, these cases should be rare, as the components chosen for the HR-
16 are based on the industry "standards" that most manufacturers adhere to.
While we have heard many complaints regarding tape back up, we have actually found very
few actual tape failures. Most of the complaints arise from user error, so below is a list of successful
backup and tape sync strategies.
1. When attempting to save to a stereo cassette deck, use only the 1 channel (using both channels
may result in odd phase cancellations during playback).
2. Avoid using any noise reduction systems (i.e. Dolby, or DBX) as these can distort the timing of
the pulse train that contains the data.