Cirrus Logic CS160x - Manual (Page 8)

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3.3.3 Option 3
This is very similar to option 2, but in this case, a 33 pF capacitor is added in parallel to a 4.7 uF VDD
decoupling capacitor. This guarantees that the ZCD decoupling capacitor cannot provide a low-
impedance path for high-frequency gate currents due to the presence of the additional VDD 33 pF
capacitor.
Option 2 and option 3 provide a clean ground for the CS pin. The ground can be continued under the IC
and the CS decoupling capacitor can be placed below the IC and decoupled close to the pin itself. This is
shown clearly in Figure 9.
Figure 9 demonstrates the best trade-off between signal integrity, manufacturability, and utility.
Figure 9. Decoupling Option 3 — Better Performance
3.3.4 Option 4
This provides the quietest layout for the ZCD pin since the ZCD capacitor is placed away from the gate-
GND current loop. Because the ZCD current is low, the distance between the ZCD ground capacitor and
the ground pin of the IC does not affect signal integrity.
The ground return of the CS pin should be decoupled away from the ground return of the ZCD pin. In this
arrangement, it is reasonable to use the ZCD ground region for decoupling the remainder of the sense
signals, such as IAC, IFB, and CS. The trace running from the back side should be as wide as possible
to ensure low-impedance.
Figure 10. Decoupling Option 4 — Best Performance