Cirrus Logic CDB42448 - Manual

Copyright © Cirrus Logic, Inc. 2004
(All Rights Reserved)
Cirrus Logic, Inc.
www.cirrus.com
CDB42448
Evaluation Board For CS42448
Features
z Single-ended/Single-ended to Differential
Analog Inputs
z Single-ended/Differential to Single-ended
Analog Outputs
z CS8406 S/PDIF Digital Audio Transmitter
z CS8416 S/PDIF Digital Audio Receiver
z Header for Optional External Software
Configuration of CS42448
z Header for External DSP Serial Audio I/O
z 3.3 V Logic Interface
z Pre-defined Software Scripts
z S/PDIF-to-TDM Conversion for Easy
Evaluation of the TDM Digital Interface
z Demonstrates Recommended Layout and
Grounding Arrangements
z Windows ® Compatible Software Interface to
Configure CS42448 and Inter-board
Connections
ORDERING INFORMATION
CDB42448 Evaluation Board
Description
The CDB42448 evaluation board is an excellent means
for evaluating the CS42448 CODEC. Evaluation re-
quires an analog/digital signal source and analyzer, and
power supplies. A Windows
®
PC compatible computer
must be used to evaluate the CS42448.
System timing for the I²S, Left-Justified and Right-Justi-
fied interface formats can be provided by the CS42448,
by the CS8416, or by a DSP I/O stake header with a DSP
connected. System timing for TDM mode is provided by
an FPGA using clocks derived from the CS8416 or DSP
I/O header.
RCA phono jacks are provided for the CS42448 analog
inputs and outputs. Digital data I/O is available via RCA
phono or optical connectors to the CS8416 and CS8406.
The Windows
®
software provides a GUI to make config-
uration of the CDB42448 easy. The software
communicates through the PC’s serial port to configure
the control port registers so that all features of the
CS42448 can be evaluated. The evaluation board may
also be configured to accept external timing and data
signals for operation in a user application during system
development.
I
CS42448
CS8416
S/PDIF
Input
y Differential to
Single-Ended
Output
y Single-Ended
Output
y Single-Ended to
Differential Input
y Single-Ended
Input
Serial Control Port
FPGA
CS8406
S/PDIF
Output
DSP HEADER
CS5341
Osc.
ANALOG INPUT
ANALOG OUTPUT
y Single-Ended
Input
AUXILIARY
ANALOG INPUT
MCLK Divided
Clocks
/Data
Hardware
Setup
MCLK BUS
A D C/DA
C Cl
oc
k s &
D a ta
ADC/DAC
Clocks/
Data
Cl
oc
k
s /D
ata
I 2 C/SPI Header
OCT ‘04
DS648DB2