Cirrus Logic CDB4245 - Manual (Page 9)

CDB4245
DS656DB1 9
4.3 Register Maps Tab
The Register Maps tab provides low level control over the register level settings of the CS4245, CS8416,
CS8406, and FPGA. Each device is displayed on a separate tab. Register values can be modified bit-wise
or byte-wise. For bit-wise, click the appropriate push button for the desired bit. For byte-wise, the desired
hex value can be typed directly in the register address box in the register map.
4.4 Pre-Configured Script Files
Pre-configured script files are provided with the CDB4245 to allow easy initial board bring-up. The board
configurations stored within these files are described in sections 4.4.1 - 4.4.2.
4.4.1 Oscillator Clock - ADC Ch 1 to DAC & SPDIF Out
Using the pre-configured script file named “Oscillator Clock - ADC Ch 1 to DAC & SPDIF Out.txt”, an analog
input signal applied to channel 1 of the CS4245 input multiplexer will be digitized by the ADC, transmitted
in S/PDIF format by the CS8406, and will be converted to analog by the CS4245 DAC and output through
the passive output filter and RCA jacks.
The CS4245 is in synchronous mode, with Oscillator 1 as the source of MCLK for Clock Domain 1 and 2.
The CS4245 Serial Audio Port 1 is the sub-clock master to both the CS4245 Serial Audio Port 2, and the
CS8406.
Figure 3. Register Maps Tab