Cirrus Logic CDB4270 - Manual (Page 5)

DS686DB3 5
CDB4270
1. SYSTEM OVERVIEW
The CDB4270 evaluation board is an excellent tool for evaluating the CS4270 CODEC. The board features both
analog and digital audio interfaces along with an FPGA for data/clk routing and an on-board microprocessor for con-
figuration control. The board is easily configured in Software Mode using the supplied PC-to-DUT USB cable along
with the Windows-based GUI configuration software or in Hardware Mode using the on-board dip switches.
The CDB4270 schematic set has been partitioned into nine pages and is shown in Figures 66 through 74 .
1.1 Power
Power must be supplied to the evaluation board through the +5.0 V binding posts. The +5 V inputs must be
referenced to the single black binding post ground connector (
Figure 74 on page 45 ).
WARNING: Please refer to the CS4270 data sheet for allowable voltage levels.
1.2 Grounding and Power Supply Decoupling
To optimize performance, PC board designs for the CS4270 require careful attention to power supply,
grounding and signal routing arrangements.
Figure 65 on page 36 shows the basic component/signal inter-
connect for the CDB4270. Figure 75 on page 46 shows the component placement. Figure 76 on page 47
shows the top layout. Figure 77 on page 48 shows the bottom layout. The decoupling capacitors are located
as close to the CS4270 as possible. Extensive use of ground plane fill in the evaluation board yields large
reductions in radiated noise.
1.3 FPGA
See “FPGA Overview” on page 9 for a complete description of the FPGA ( Figure 72 on page 43 ) that is used
on the CDB4270.
1.4 CS4270 Audio CODEC
A complete description of the CS4270 ( Figure 66 on page 37 ) is included in the CS4270 product data sheet.
The CS4270 codec performs stereo 24-bit A/D and D/A conversion at sample rates of up to 216 KHz. The
part accommodates I²S, Left-Justified and Right-Justified serial audio formats.
1.5 CS8406 Digital Audio Transmitter
A complete description of the CS8406 transmitter ( Figure 69 on page 40 ) and a discussion of the digital au-
dio interface are included in the CS8406 data sheet.
The CS8406 converts the PCM data from either the CS4270, the DSP Header, or the CS8416 to a standard
S/PDIF data stream. The CS8406 operates in either master or slave sub-clock mode and will accept either
a 128 Fs, 256 Fs, or 512 Fs master clock on the OMCK input pin. The device will operate in either the Left-
Justified or I²S interface data modes.
1.6 CS8416 Digital Audio Receiver
A complete description of the CS8416 receiver ( Figure 70 on page 41 ) and a discussion of the digital audio
interface are included in the CS8416 data sheet.
The CS8416 converts the input S/PDIF data stream into PCM data that can be used by the CS4270 and
CS8406. The device operates in either Master or Slave sub-clock modes and generates either a 128 Fs or
256 Fs master clock for output on the RMCK pin. Either Left-Justified or I²S interface output data formats
can be selected