Cirrus Logic CS4297A - Manual (Page 27)

CS4297A
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4.13 Powerdown Control/Status Register (Index 26h)
EAPD External Amplifier Power Down. The EAPD pin follows this bit and is generally used to power
down external amplifiers.
PR6 Alternate Line Out Powerdown. When ‘set’, the alternate line out buffer is powered down.
PR5 Internal Clock Disable. When ‘set’, this bit completely powers down both the analog and digital
sections of the CS4297A. The only way to recover from setting this bit is through a Cold Reset
(driving the RESET# signal active).
PR4 AC-link Powerdown. When ‘set’, the AC link is powered down (BIT_CLK off). The AC-link can
be restarted through a Warm Reset using the SYNC signal, or a Cold Reset using the RESET#
signal (primary audio codec only).
PR3 Analog Mixer Powerdown (Vref off). When ‘set’, the analog mixer and voltage reference are
powered down. When clearing this bit, the ANL, ADC, and DAC bits should be checked before
writing any mixer registers.
PR2 Analog Mixer Powerdown (Vref on). When ‘set’, the analog mixer is powered down (the voltage
reference is still active). When clearing this bit, the ANL bit should be checked before writing
any mixer registers.
PR1 Front DACs Powerdown. When ‘set’, the DACs are powered down. When clearing this bit, the
DAC bit should be checked before sending any data to the DACs.
PR0 L/R ADCs and Input Mux Powerdown. When ‘set’, the ADCs and the ADC input muxes are pow-
ered down. When clearing this bit, no valid data will be sent down the AC link until the ADC bit
goes high.
REF Voltage Reference Ready Status. When ‘set’, indicates the voltage reference is at a nominal
level.
ANL Analog Ready Status. When ‘set’, the analog output mixer, input multiplexer, and volume con-
trols are ready. When clear, no volume control registers should be written.
DAC Front DAC Ready Status. When ‘set’, the DACs are ready to receive data across the AC link.
When clear, the DACs will not accept any valid data.
ADC L/R ADC Ready Status. When ‘set’, the ADCs are ready to send data across the AC link. When
clear, no data will be sent to the Controller.
Default 0000h. This value indicates all blocks are powered on. The lower four bits will change as the
CS4297A finishes an initialization and calibration sequence.
The PR[6:0] and the EAPD bits are powerdown control for different sections of the CS4297A as well as external
amplifiers. The REF, ANL, DAC, and ADC bits are read-only status bits which, when ‘set’, indicate that a particular
section of the CS4297A is ready. After the controller receives the Codec Ready bit in input Slot 0, these status bits
must be checked before writing to any mixer registers. See Section 5, Power Management, for more information on
the powerdown functions.
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0 0 0 0 0 REF ANL DAC ADC
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CS4297A