Cirrus Logic CS4360 - Manual (Page 17)

CS4360
DS517F2 17
SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE
Inputs: Logic 0 = GND, Logic 1 = VLC
Notes: 7. Data must be held for sufficient time to bridge the transition time, t
fc
, of SCL.
8. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
9. for Single-Speed Mode, for Double-Speed Mode, for Quad-Speed Mode.
Parameter Symbol Min Max Unit
I²C Mode
SCL Clock Frequency f
scl
- 100 kHz
RST Rising Edge to Start t
irs
500 - ns
Bus Free Time Between Transmissions t
buf
4.7 - µs
Start Condition Hold Time (prior to first clock pulse) t
hdst
4.0 - µs
Clock Low time t
low
4.7 - µs
Clock High Time t
high
4.0 - µs
Setup Time for Repeated Start Condition t
sust
4.7 - µs
SDA Hold Time from SCL Falling (Note 7) t
hdd
0 - µs
SDA Setup time to SCL Rising t
sud
250 - ns
Rise Time of SCL and SDA t
rc
, t
rc
- 1 µs
Fall Time SCL and SDA t
fc
, t
fc
- 300 ns
Setup Time for Stop Condition t
susp
4.7 - µs
Acknowledge Delay from SCL Falling (Note 8) t
ack
- (Note 9) ns
5
256 Fs
×
---------------------
5
128 Fs
×
---------------------
5
64 Fs
×
------------------
t
b uf t
h ds t
t
l o w
t
hd d
t
high
t
s u d
S to p S t a r t
S D A
S C L
t
irs
R S T
t
h d st
t
rc
t
fc
t sust
t susp
S t a r t S to p
R e p e a t e d
t
rd
t
fd
t
a c k
Figure 13. Control Port Timing - I²C Mode