Cirrus Logic CS4373A - Manual (Page 16)

CS4373A
16 DS699F2
2. GENERAL DESCRIPTION
The CS4373A is a differential output digital-to-
analog converter with multiple operational
modes and programmable output attenuation.
It provides self-test and precision calibration
capability for high-resolution, low-frequency
measurement systems designed from
CS3301A / CS3302A differential amplifiers,
CS5371A / CS5372A
∆Σ modulators, and the
CS5376A digital filter.
2.1 Digital Inputs
The CS4373A is driven by a
∆Σ digital bit
stream from the CS5376A digital filter test bit
stream (TBS) generator. The digital filter also
provides clock and sync signals as well as
GPIO control signals to set the operational
mode and attenuation.
2.2 Analog Outputs
Two sets of differential analog outputs, OUT
and BUF, simplify system design as dedicated
outputs for testing the electronics channel and
for in-circuit sensor tests. Output attenuator
settings are binary weighted (1, 1/2, 1/4, 1/8,
1/16, 1/32, 1/64) and match the
CS3301A / CS3302A amplifier input levels for
full-scale testing at all gain ranges.
For maximum performance, the precision out-
puts (OUT±) must drive only high-impedance
loads such as the CS3301A / CS3302A ampli-
fier inputs. The buffered outputs (BUF±) can
drive lower-impedance loads, down to 1 k
Ω,
but with reduced performance compared to
the precision outputs.
2.3 Multiple Operational Modes
The CS4373A operates in either AC or DC test
modes. AC test modes (MODE 1, 2, 3, 6) are
used to measure system THD and CMRR per-
formance. DC test modes (MODE 4, 5) are for
gain calibration and pulse tests.
2.4 Low Power
The CS4373A is optimized for low-power op-
eration and has a restricted operational band-
width in the AC modes. For stable operation,
full-scale AC test signals must not contain fre-
quencies above 100 Hz. AC test signals above
100 Hz (TBS impulse mode, for example)
must have a -20 dB reduced amplitude to en-
sure stability of the CS4373A low-power
∆Σ ar-
chitecture.
24-Bit ∆Σ
DAC
Attenuator
Clock
Generator
TDATA
VA+ MODE(0, 1, 2) ATT(0, 1, 2) VD
VA-
VREF+
VREF-
GND
OUT+
OUT-
BUF+
BUF-
CAP+ CAP-
MCLK
MSYNC
Figure 4. CS4373A Block Diagram