Cirrus Logic CS4953xx - Manual (Page 36)

I2C Port
CS4953xx Hardware User’s Manual
DS732UM10 Copyright 2010 Cirrus Logic, Inc 3-4
3.3.2 I
2
C Bus Dynamics
The Start condition for an I
2
C transaction is defined as the first falling edge on the SCP1_SDA line while
SCP1_CLK is high. An I
2
C Stop condition is defined as the first rising edge on the SCP1_SDA line while
SCP1_CLK is high. Hence for valid data transfer, SCP1_SDA must remain stable during the high period of
the clock pulse. Start and Stop conditions are always generated by the master. The bus is considered to
be busy after the Start condition. The bus is considered to be free again following the Stop condition. The
bus stays busy if a repeated Start condition is generated instead of a Stop condition. In this respect, the
Start and repeated Start conditions are functionally identical.
Figure 3-3. I
2
C Start and Stop Conditions
SCP2_CLK
I
2
C Control Port Bit Clock.
In master mode, this pin serves as the serial control clock
output (open drain in I 2 C mode / output in SPI mode). In
serial slave mode, this pin serves as the serial control
clock input. In I
2
C slave mode the clock can be pulled low
by the port to stall the master.
103 1
Open
Drain
SCP2_SDA
Bidirectional Data I
2
C Mode Master/Slave Data IO. In I
2
C
master and slave mode, this open drain pin serves as the
data input and output. 105 2
Open
Drain
SCP2_IRQ
Serial Control Port Data Ready Interrupt Request, Output,
Active Low.
This pin is driven low when the DSP has a message for
the host to read. The pin will go high when the host has
read the message and the DSP has no further messages.
108 5
Open
Drain
Table 3-1. Serial Control Port 1 I
2
C Signals (Continued)
Pin Name Pin Description
LQFP-144
Pin #
LQFP-128
Pin #
Pin
Type
SCP1_CLK
SCP1_SDA
Start
SCP1_CLK
SCP1_SDA
Stop