Cirrus Logic AN299 - Manual (Page 2)

2 AN299REV1
AN299
Figure 2. Preferred Layout for Minimizing Differential Noise from the Ground Plane
As illustrated in Figure 2 , if a high-speed signal return path or power supply return path flows through the ground
plane in such a way that introduces a noise voltage drop between the point where two capacitors, one on AIN+ and
one on AIN-, connect to the ground plane, a differential noise voltage will be inadvertently applied to the ADC input
through those capacitors.
This does not necessarily mean that, in order to avoid voltage drops across the plane, one should avoid using a
common ground plane for both digital and analog circuitry The debate about whether digital ground and analog
ground should be separated has gone on for years but one thing remains indisputable –
the digital ground (DGND)
pin and any other pin on the ADC that connects to analog ground must be tied together at the ADC via a very low-
impedance path. This includes bypass capacitors on the power pins and anti-aliasing and filter capacitors on the
AIN and VREF pins. If separate DGND and analog ground (AGND) planes are used, they must be tied together be-
neath the ADC. Also, take great care to prevent clock or high-speed digital signal traces from crossing splits in the
ground plane (or splits in an adjacent power plane). The problem with split or non-continuous planes is that high-
speed return currents tend to return to the source in a path that is as close to the active trace as possible. However,
discontinuities in the adjacent ground or power plane force the currents to deviate from that path. This deviation re-
sults in “antenna” loops that radiate high-frequency energy as illustrated in
Figure 3 . Once these signals are radiated
it is very difficult to prevent them from being picked up by the sensitive analog inputs.
In this layout C1, C2, and C3 are connected to the ground plane with
three separate vias which may have noise voltage deltas among
them. This layout is preferred because all three capacitors are connected to
the ground plane with one via so there can be no noise voltage delta
present.