Cirrus Logic AN273 User Manual
Cirrus Logic Hardware
Copyright
© Cirrus Logic, Inc. 2007
(All Rights Reserved)
AN273
EP93xx Silicon Rev E
Design Guidelines
1. Introduction
This document is intended to inform customers using EP93xx Rev E0/E1/E2 devices in their designs of certain
important considerations. The recommendations contained in this document are lesser-known requirements of the
EP93xx devices. Unless otherwise noted, these guidelines apply for all EP93xx Rev E devices.
This document should be used in conjuction with the particular EP93xx device data sheet and/or user’s guide.
2. Real Time Clock (RTC)
A real time clock (RTC) signal is required to be connected to the EP93xx device. This clock is used by
internal logic to boot the device. The EP93xx device will not power up if there is no connection to the
EP93xx RTC clock pin(s).
3. RTC External Oscillator Circuit
An external RTC oscillator circuit is required to ensure proper EP93xx power-up and RTC time tracking
accuracy. The circuit must provide a clean, symmetrical square wave. For the recommended RTC circuit
design, please refer to AN265, which can be found at:
4. External Memory Configuration
A problem exists when performing a Sync boot (ADSO=1 when reset is released) with the 32-bit EP93xx
device using 16-bit Flash memory and 32-bit SDRAM connected to SDCS3.
The EP93xx devices were originally designed to support booting from Synchronous Flash devices such
as the AT49LD3200 or the MT28S4M16LCTG-10. These Sync Flash devices were designed to be ac-
cessed by an SDRAM controller. They behaved like SDRAM but were actually Flash devices. If one of
these Sync Flash devices was used, it was intended to be connected to SDCS3. That way, the boot con-
figuration would apply the boot memory width to SDCS3. These Sync Flash devices that the EP93xx de-
vice was originally designed to use are no longer produced. The EP93xx devices do not support the newer
Sync Flash devices like the K3 product offered from Intel Corporation.
The EP93xx device latches the state of ASD0 and nCS[7:6] upon reset, along with several other signals.
If ASD0 is sampled high, Sync boot mode is selected. The EP93xx swaps the address map for nCS0 with
nSDCS3. Bits nCS[7:6] specify the data bus width of the boot memory device. Refer the appropriate
EP93xx User's Guide for more detail on boot modes.
FEB ‘07
AN273REV4