Vicor PI33XX-XX Multi-Phase Design Guide User Manual

Cool-power, Pi33xx-xx, Multi-phase design guide

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vicorpower.com Rev 1.0

Cool-Power

®

800 735.6200 11/2012 Page 1 of 4

Cool-Power

®

PI33XX-XX

Multi-Phase Design Guide

Description

The Multi-Phase Design Guide provides an overview
to paralleling two or three PI33XX-XX devices
together without any change required to the basic
single-phase power stage or compensation design.
Paralleling multiple PI33XX modules increases the
output current capability and reduces the output
voltage ripple. For information on paralleling more
than three regulators, please contact Picor.

Basic Connections

The PI33XX family of Cool-Power products employs a
ZVS topology which operates exclusively in
discontinuous

and

critical

conduction

mode.

Therefore, to derive real-time output current
information, each device’s error amplifier output
(EAO) is trimmed to a nominal level (2.2V) when
supporting the maximum rated output load. This will
allow the EAO to track the output load. By trimming
the EAO this way, additional regulators can be
connected in parallel to deliver equal amount of
current to a single regulated point by linking each
regulator’s EAO pin together. The basic pin
connections needed to parallel two or three
regulators are shown in Figure 1. The SYNCO pins are
for phase synchronization, TRK is for soft-start and
fault shutdown tracking. EAO is for current sharing
between phases.

Two and Three Phases

The PI33XX-2X can be synchronized in a closed loop
configuration to up to three phases by adding an
additional 2.5kΩ (R1) feedback resistor to the design
and incorporating the PGD pin.

Figure 1 – Basic Connections for Parallel Operation

This method will allow the regulators to remain in
synchronization when the system’s operational
frequency stretches at high output loads. Figure 2
shows the basic synchronization connections and the
phase requiring delays in red.

Figure 2 - SYNCI (In) and SYNCO (Out) Connection for

Two and Three Phase Design

1

out

i

n

i

n

i

n

R1

out

out

PGD

out

i

n

i

n

R1

out

PGD

1

2

3

2

(a)

(b)

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