Cypress CY7C1041DV33 - Manual

Cypress Semiconductor Corporation • 198 Champion Court • San Jose
,
CA 95134-1709 • 408-943-2600
Document #: 38-05473 Rev. *E Revised July 17, 2008
CY7C1041DV33
4 Mbit (256K x 16) Static RAM
Features
■ Pin and function compatible with CY7C1041CV33
■ High speed
❐ t
AA
= 10 ns
■ Low active power
❐ I
CC
= 90 mA at 10 ns (industrial)
■ Low CMOS standby power
❐ I
SB2
= 10 mA
■ 2.0V data retention
■ Automatic power down when deselected
■ TTL compatible inputs and outputs
■ Easy memory expansion with CE and OE features
■ Available in Pb-free 48-ball VFBGA, 44-pin (400-mil) molded
SOJ, and 44-pin TSOP II packages
Functional Description
The CY7C1041DV33 [1] is a high performance CMOS Static RAM
organized as 256K words by 16 bits. To write to the device, take
Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte
LOW Enable (BLE) is LOW, then data from IO pins (IO
0
to IO
7
)
is written into the location specified on the address pins (A
0
to
A
17
). If Byte HIGH Enable (BHE) is LOW, then data from IO pins
(IO
8
to IO
15
) is written into the location specified on the address
pins (A
0
to A
17
).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
BLE is LOW, then data from the memory location specified by
the address pins appears on IO
0
to IO
7
. If BHE is LOW, then data
from memory appears on IO
8
to IO
15
. See the Truth Table on
page 9 for a complete description of read and write modes.
The input and output pins (IO
0
to IO
15
) are placed in a high
impedance state when the device is deselected (CE HIGH),
outputs are disabled (OE HIGH), BHE and BLE are disabled
(BHE, BLE HIGH), or during a write operation (CE LOW and WE
LOW).
The CY7C1041DV33 is available in a standard 44-pin 400-mil
wide SOJ and 44-pin TSOP II package with center power and
ground (revolutionary) pinout and a 48-ball fine-pitch ball grid
array (FBGA) package.
14 15
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
RO
W DE
CO
DE
R
S
E
N
SE AM
PS
INPUT BUFFER
256K × 16
A
0
A
11
A
13
A
12
A A A
16
A
17
A
9
A
10
IO
0
–IO
7
OE
IO
8
–IO
15
CE
WE
BLE
BHE
Logic Block Diagram
Note
1. For guidelines on SRAM system design, refer to the “System Design Guidelines” Cypress application note, available at www.cypress.com.
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