Calibre UK UCA93 - Manual (Page 21)

CALIBRE
Issue 1.0 Page 18
01/07/03
Appendix A I 2 C Communications Adapter Status Codes
This is an eight bit register, read using the GetStatus routine. Each individual bit has its own meaning as
follows:
Bit 7 (MSB) - The (old) PIN Bit
To all intents and purposes, this bit is now redundant. Previous Calibre I2C products used this bit to
synchronise data transfers between the I2C bus and the host PC. On the UCA93 synchronisation is
achieved by the Adapter returning a status byte to the host when the requested function has completed
or timed out. Whereas the value of the PIN bit used to be important, now it is whether or not the status
byte has been returned to the host that is important. The PIN bit roughly mimics the behaviour of the
old products so that customers still feel comfortable with it, but software should not rely on it. Other bits
in the status word are still important, and should be interpreted as below.
Bit 6 – The Timeout Bit Normally this bit should read as a 0. If it is set the Adapter timed out when
attempting some master activity. This could mean that another master has control of the bus or that a
bus error has occurred or that a slave device is seriously slowing down the bus. Timeout normally
occurs about 500uS after a master function is requested. This is a new bit which was not implemented
on previous generations of Calibre products.
Bit 5 - The (old) STS Bit
This bit normally reads as a 0 and is set this way only as legacy support. On previous Calibre I2C
products indicated that a stop had been detected whilst in slave receiver mode. Software should not rely
on this bit.
Bit 4 - The BER (Bus Error) Bit
This bit should normally read as a 0. It is set high when a misplaced Start or Stop has been detected.
This can be quite serious since the I
2 C devices on the bus may be left in an undefined state after a bus
error has occurred - in some circumstances the only way to get the bus going again may be to reset all
the I
2 C devices on it.
Bit 3 - The Ack Bit
This bit indicates the state of the 9 th I2C bit which is the acknowledge bit. It is active low so reads as 0
for if the receiver acknowledged and 1 if the receiver did not acknowledge. In a master SendAddress or
Restart function it indicates whether the slave is present or not. In a master write operation it indicates
whether the slave acknowledged the data byte or not, in a master read it indicates whether or not the
master was requested to acknowledge the data from the slave or not.
Bit 2 - The (old) AAS Bit
This bit should normally read as a 0 and is set this way for legacy support. On previous Calibre I2C
products indicated that a device had been addressed whilst in a slave mode. Software should not rely
on this bit.
Bit 1 - The LAB (Lost Arbitration) Bit
This bit should read as a 0. It is set = 1 when, in multimaster operation (more than one master present
on the I
2 C bus) arbitration is lost to another master on the I 2 C bus.
Bit 0 - The BB (Bus Busy) Bit
This bit reads as a 1 when the bus is idle. Once a Start has been detected it goes low and stays low
until the transfer is terminated correctly with a Stop. New transmissions should therefore not be
attempted if this bit is low – it may be that another master has control. If there is no other master on the
system it may be that a slave is stuck or a bus error has occurred in which case a Recover may free up
the bus.