Compaq COBOL AAQ2G1FTK - Manual (Page 493)

Optimizing Your Compaq COBOL Program
15.1 Specifying Optimization on the Compiler Command Line
• EV6—Generates and schedules code for the 21264 chip implementation
that uses the following extensions to the base Alpha instruction set: BWX
(Byte/Word manipulation) and MAX (Multimedia) instructions, square root
and FIX (Floating-point convert) instructions, and CIX (Count) instructions.
• EV67—Generates and schedules code for the 21264A chip implementation
that uses the following extensions to the base Alpha instruction set: BWX
(Byte/Word manipulation) and MAX (Multimedia) instructions, square root
and FIX (Floating-point convert) instructions, and CIX (Count) instructions.
• PCA56—Generates code for the 21164PC chip implementation that uses
the byte and word manipulation instruction extensions and multimedia
instruction extensions of the Alpha architecture.
Running programs compiled with the PCA56 keyword may incur emulation
overhead on EV4, EV5, and EV56 processors, but will still run correctly on
OpenVMS Version 7.1 (or later) systems.
/ARCHITECTURE Qualifier
The /ARCHITECTURE= option qualifier (or -arch option on Tru64 UNIX)
determines the type of Alpha chip code that will be generated for a particular
program.
The /ARCHITECTURE qualifier uses the same options (keywords) as the
/OPTIMIZE=TUNE qualifier, and their definitions are similar. However, their
effects are not identical. The /OPTIMIZE=TUNE qualifier is primarily used by
certain higher-level optimizations for instruction scheduling purposes, while the
/ARCHITECTURE qualifier determines the type of code instructions generated
for the program unit being compiled.
OpenVMS Version 7.1 and subsequent releases provide an operating system
kernel that includes an instruction emulator. This emulator allows new
instructions, not implemented on the host processor chip, to execute and produce
correct results. All Alpha processors implement a core set of instructions. Certain
Alpha processor versions include additional instruction extensions. Applications
using emulated instructions will run correctly, but might incur significant
software emulation overhead at run time.
The following /ARCHITECTURE options are supported:
• GENERIC—Generates code that is appropriate for all Alpha processor
generations. This is the default.
Programs compiled with the GENERIC option run all implementations of the
Alpha architecture without any instruction emulation overhead.
• HOST—Generates code for the processor generation in use on the system
being used for compilation.
Programs compiled with this option on other implementations of the Alpha
architecture may encounter instruction emulation overhead.
• EV4—Generates code for the 21064, 21064A, 21066, and 21068
implementations of the Alpha architecture.
Programs compiled with the EV4 option run without instruction emulation
overhead on all Alpha processors.
• EV5—Generates code for some 21164 chip implementations of the Alpha
architecture that use only the base set of Alpha instructions (no extensions).
Programs compiled with the EV5 option run without instruction emulation
overhead on all Alpha processors.
Optimizing Your Compaq COBOL Program 15–3