Cypress CY7C1006D User Manual

Mbit (256k x 4) static ram, Features, Functional description

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1-Mbit (256K x 4) Static RAM

CY7C106D

CY7C1006D

Cypress Semiconductor Corporation

198 Champion Court

San Jose

,

CA 95134-1709

408-943-2600

Document #: 38-05459 Rev. *E

Revised February 22, 2007

Features

• Pin- and function-compatible with CY7C106B/CY7C1006B
• High speed

— t

AA

=

10 ns

• Low active power

— I

CC

= 80 mA @ 10 ns

• Low CMOS standby power

— I

SB2

= 3.0 mA

• 2.0V Data Retention
• Automatic power-down when deselected
• CMOS for optimum speed/power
• TTL-compatible inputs and outputs
• CY7C106D available in Pb-free 28-pin 400-Mil wide Molded

SOJ package. CY7C1006D available in Pb-free 28-pin
300-Mil wide Molded SOJ package

Functional Description

[1]

The CY7C106D and CY7C1006D are high-performance
CMOS static RAMs organized as 262,144 words by 4 bits.
Easy memory expansion is provided by an active LOW Chip
Enable (CE), an active LOW Output Enable (OE), and tri-state
drivers. These devices have an automatic power-down feature
that reduces power consumption by more than 65% when the
devices are deselected. The four input and output pins (IO

0

through IO

3

) are placed in a high-impedance state when:

• Deselected (CE HIGH)
• Outputs are disabled (OE HIGH)
• When the write operation is active (CE and WE LOW)

Write to the device by taking Chip Enable (CE) and Write
Enable (WE) inputs LOW. Data on the four IO pins (IO

0

through IO

3

) is then written into the location specified on the

address pins (A

0

through A

17

).

Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins appears on the four IO pins.

Logic Block Diagram

IO0
IO1
IO2
IO3

SENSE AMPS

POWER

DOWN

CE

WE

OE

A1

A2

A3

A4

A5

A6

A7

A8

A9

ROW DECODER

256K x 4

ARRAY

INPUT BUFFER

A

0

A

10

A

11

A

12

A

13

A

14

A

15

A

16

A

17

COLUMN DECODER

Note

1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at

www.cypress.com

.

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