Cypress CY7C0430BV User Manual
Page 28
CY7C0430BV
CY7C0430CV
Document #: 38-06027 Rev. *B
Page 28 of 37
number of TCK cycles depending on the TCK and CLKBIST
frequency.
t
CYC
is total number of TCK cycles required to run MBIST.
SPC is the Synchronization Padding Cycles (4–6 cycles).
m is a constant represents the number of read and write opera-
tions required to run MBIST algorithms (31195136).
Once the entire MBIST sequence is completed, supplying
extra TCK or CLKBIST cycles will have no effect on the MBIST
controller state or the pass-fail status.
Debug Mode
With the CYBIST instruction loaded and the MCR loaded with
the value of “01,” and the FSM transitions to RUN_TEST/IDLE
state, the MBIST goes into CYBIST-debug mode. The debug
mode will be used to provide complete failure analysis infor-
mation at the board level. It is recommended that the user runs
the non-debug mode first and then the debug mode in order to
save test time and to set an upper bound on the number of
scan outs that will be needed. The failure data will be scanned
out automatically once a failure occurs using the JTAG TAP
interface. The failure data will be represented by a 100-bit
packet given below. The 100-bit Memory Debug Register
(MDR) will be connected between TDI and TDO, and will be
shifted out on TDO, which is synchronized to TCK.
Figure 3 is a representation of the 100-bit MDR packet. The
packet follows a two-bit header that has a logic “1” value, and
represents two TCK cycles. MDR[97:26] represent the BIST
comparator values of all four ports (each port has 18 data
lines). A value of “1” indicates a bit failure. The scanned out
data is from LSB to MSB. MDR[25:10] represent the failing
address (MSB to LSB). The state of the BIST controller is
scanned out using MDR[9:4]. Bit 2 is the Test Done bit. A “0”
in bit 2 means test not complete. The user has to monitor this
bit at every packet to determine if more failure packets need to
be scanned out at the end of the BIST operations. If the value
is “0” then BIST must be repeated to capture the next failing
packet. If it is “1,” it means that the last failing packets have
been scanned out. A trailer similar to the header represents
the end of a packet.
MCR_SCAN
This instruction will connect the Memory BIST Control
Register (MCR) between TDI and TDO. The default value
(upon master reset) is “00.” Shift_DR state will allow modifying
the MCR to extend the MBIST functionality.
MBIST Control States
Thirty-five states are listed in Table 7. Four data algorithms are
used in debug mode: moving inversion (MIA), march_2 (M2A),
checkerboard (CBA), and unique address algorithm (UAA).
Only Port 1 can write MIA, M2A, and CBA data to the memory.
All four ports can read any algorithm data from the QuadPort
DSE device memory. Ports 2, 3, and 4 will only write UAA data.
Boundary Scan Cells (BSC)
Table 9 lists all QuadPort DSE family I/Os with their associated
BSC. Note that the cells have even numbers. Every I/O has
two boundary scan cells. Bidirectional signals (address lines,
datalines) require two cells so that one (the odd cell) is used
to control a three-state buffer. Input only and output only
signals have an extra dummy cell (odd cells) that are used to
ease device layout.
t
CYC
t
CYC
CLKBIST
[
]
t
CYC
TCK
[
]
-------------------------------------------- m SPC
+
×
=
1
1
1
1
97
99
98
P4_IO(17-9)
P3_IO(17-9)
P1_IO(17-9)
P2_IO(17-9)
P4_IO(8-0)
P3_IO(8-0)
P1_IO(8-0)
P2_IO(8-0)
A(15-0)
MBIST_State
P/F
62
61
26
25
10
9
4
3
2
1
0
TD
Figure 3. MBIST Debug Register Packet